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公开(公告)号：US09274973B2
公开(公告)日：2016-03-01
申请号：US14269445
申请日：2014-05-05
Applicant: Micron Technology, Inc.
Inventor： Troy A. Manning , Martin L. Culley , Troy D. Larsen
CPC classification number: G06F12/1045 , G06F12/0246 , G06F12/0292 , G06F12/1009 , G06F12/1027 , G06F2212/1004 , G06F2212/7201 , Y02D10/13
Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.
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公开(公告)号：US09088303B2
公开(公告)日：2015-07-21
申请号：US13780726
申请日：2013-02-28
Applicant: Micron Technology, Inc.
Inventor： Troy D. Larsen , Martin L. Culley
CPC classification number: G06F11/1068 , G11C29/52 , H03M13/09 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/2906
Abstract: The present disclosure includes apparatuses and methods for codewords that span pages of memory. A number of methods include writing a first portion of a primary codeword to a first page in a first block of memory and writing a second portion of the primary codeword to a second page in a second block of memory. The primary codeword can be included in a secondary codeword. The method can include writing a first portion of the secondary codeword in the memory and writing a second portion of the secondary codeword to a different page and block of the memory than the first portion of the secondary codeword.
Abstract translation: 本公开包括跨越存储器页面的码字的装置和方法。 许多方法包括将主码字的第一部分写入第一存储器块中的第一页，并将主码字的第二部分写入第二存储器块中的第二页。 主码字可以被包括在次码字中。 该方法可以包括将次码字的第一部分写入存储器中，并将次码字的第二部分写入与辅助码字的第一部分不同的存储器页和块。
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公开(公告)号：US20140297990A1
公开(公告)日：2014-10-02
申请号：US14269445
申请日：2014-05-05
Applicant: Micron Technology, Inc.
Inventor： Troy A. Manning , Martin L. Culley , Troy D. Larsen
IPC: G06F12/10
CPC classification number: G06F12/1045 , G06F12/0246 , G06F12/0292 , G06F12/1009 , G06F12/1027 , G06F2212/1004 , G06F2212/7201 , Y02D10/13
Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.
Abstract translation: 本公开包括用于存储器地址转换的装置，系统和方法。 一个或多个实施例包括存储器阵列和耦合到阵列的控制器。 阵列包括具有多个记录的第一表，其中每个记录包括多个条目，其中每个条目包括对应于阵列中存储的数据段的物理地址和逻辑地址。 控制器包括具有多个记录的第二表，其中每个记录包括多个条目，其中每个条目包括对应于第一表中的记录的物理地址和逻辑地址。 控制器还包括具有多个记录的第三表，其中每个记录包括多个条目，其中每个条目包括对应于第二表中的记录的物理地址和逻辑地址。
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公开(公告)号：US20140245097A1
公开(公告)日：2014-08-28
申请号：US13780726
申请日：2013-02-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Troy D. Larsen , Martin L. Culley
IPC: H03M13/29
CPC classification number: G06F11/1068 , G11C29/52 , H03M13/09 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/2906
Abstract: The present disclosure includes apparatuses and methods for codewords that span pages of memory. A number of methods include writing a first portion of a primary codeword to a first page in a first block of memory and writing a second portion of the primary codeword to a second page in a second block of memory. The primary codeword can be included in a secondary codeword. The method can include writing a first portion of the secondary codeword in the memory and writing a second portion of the secondary codeword to a different page and block of the memory than the first portion of the secondary codeword.
Abstract translation: 本公开包括跨越存储器页面的码字的装置和方法。 许多方法包括将主码字的第一部分写入第一存储器块中的第一页，并将主码字的第二部分写入第二存储器块中的第二页。 主码字可以被包括在次码字中。 该方法可以包括将次码字的第一部分写入存储器中，并将次码字的第二部分写入与辅助码字的第一部分不同的存储器页和块。
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公开(公告)号：US20200272538A1
公开(公告)日：2020-08-27
申请号：US16871641
申请日：2020-05-11
Applicant: Micron Technology, Inc.
Inventor： Troy A. Manning , Troy D. Larsen , Martin L. Culley
Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.
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Patent Agency Ranking
公开(公告)号：US09292382B2
公开(公告)日：2016-03-22
申请号：US14802005
申请日：2015-07-17
Applicant: Micron Technology, Inc.
Inventor： Troy D. Larsen , Martin L. Culley
CPC classification number: G06F11/1068 , G11C29/52 , H03M13/09 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/2906
Abstract: The present disclosure includes apparatuses and methods for codewords that span pages of memory. A number of methods include writing a first portion of a primary codeword to a first page in a first block of memory and writing a second portion of the primary codeword to a second page in a second block of memory. The primary codeword can be included in a secondary codeword. The method can include writing a first portion of the secondary codeword in the memory and writing a second portion of the secondary codeword to a different page and block of the memory than the first portion of the secondary codeword.
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公开(公告)号：US20160018993A1
公开(公告)日：2016-01-21
申请号：US14867139
申请日：2015-09-28
Applicant: Micron Technology, Inc.
Inventor： Troy A. Manning , Troy D. Larsen , Martin L. Culley , Jeffrey L. Meader , Steve G. Bard , Dean C. Eyres
IPC: G06F3/06
CPC classification number: G06F3/0608 , G06F3/0661 , G06F3/0673 , H03M7/30 , H03M7/60 , H03M7/6082
Abstract: The present disclosure includes apparatuses and methods for data compression and management. A number of methods include receiving a number of data segments corresponding to a managed unit amount of data, determining a respective compressibility of each of the number of data segments, compressing each of the number of data segments in accordance with its respective determined compressibility, forming a compressed managed unit that includes compressed and/or uncompressed data segments corresponding to the number of data segments corresponding to the managed unit amount of data, and forming a page of data that comprises at least the compressed managed unit.
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公开(公告)号：US20150324252A1
公开(公告)日：2015-11-12
申请号：US14802005
申请日：2015-07-17
Applicant: Micron Technology, Inc.
Inventor： Troy D. Larsen , Martin L. Culley
CPC classification number: G06F11/1068 , G11C29/52 , H03M13/09 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/2906
Abstract: The present disclosure includes apparatuses and methods for codewords that span pages of memory. A number of methods include writing a first portion of a primary codeword to a first page in a first block of memory and writing a second portion of the primary codeword to a second page in a second block of memory. The primary codeword can be included in a secondary codeword. The method can include writing a first portion of the secondary codeword in the memory and writing a second portion of the secondary codeword to a different page and block of the memory than the first portion of the secondary codeword.
Abstract translation: 本公开包括跨越存储器页面的码字的装置和方法。 许多方法包括将主码字的第一部分写入第一存储器块中的第一页，并将主码字的第二部分写入第二存储器块中的第二页。 主码字可以被包括在次码字中。 该方法可以包括将次码字的第一部分写入存储器中，并将次码字的第二部分写入与辅助码字的第一部分不同的存储器页和块。
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公开(公告)号：US09164701B2
公开(公告)日：2015-10-20
申请号：US14255525
申请日：2014-04-17
Applicant: Micron Technology, Inc.
Inventor： Martin L. Culley , Troy A. Manning , Troy D. Larsen
CPC classification number: G06F3/0665 , G06F12/00 , G06F12/0246 , G06F12/0292 , G06F12/04 , G06F12/10 , G06F12/1027 , G06F12/1408 , G06F12/1475 , G06F2212/7201 , G06F2212/7202 , Y02D10/13
Abstract: The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.
Abstract translation: 本公开包括用于逻辑地址转换的方法，用于操作存储器系统的方法和存储器系统。 一种这样的方法包括接收与LA相关联的命令，其中LA在LAs的特定范围内，并且使用对应于当写入与范围相关联的数据时跳过的物理位置的数量来将LA转换到存储器中的物理位置 的特定范围以外的。
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公开(公告)号：US20140325316A1
公开(公告)日：2014-10-30
申请号：US14255064
申请日：2014-04-17
Applicant: Micron Technology, Inc.
Inventor： Sampath K. Ratnam , Troy D. Larsen , Doyle W. Rivers , Troy A. Manning , Martin L. Culley
IPC: G06F11/10
CPC classification number: G06F11/1068 , G06F11/10 , G06F11/108 , G11C11/5628 , G11C16/0483
Abstract: Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location can be different than the first location with respect to the second and the first memory blocks.
Abstract translation: 跨越多个存储器块的数据保护可以包括将码字的第一部分写入第一存储器块的第一位置，并将码字的第二部分写入第二存储器块的第二位置。 第二位置可以不同于第二位置和第一存储块的第一位置。
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