Memory device and in-memory search method thereof

    公开(公告)号:US12183422B2

    公开(公告)日:2024-12-31

    申请号:US18166495

    申请日:2023-02-09

    Abstract: A memory device and an in-memory search method thereof are provided. The in-memory search method includes: providing, in a first stage, a first voltage or a second voltage to a word line of at least one target memory cell according to a logical status of searched data, and reading a first current; providing, in a second stage, a third voltage or a fourth voltage to the word line of the at least one target memory cell according to the logical status of the searched data, and reading a second current; and obtaining a search result according to a difference between the second current and the first current.

    Method for manufacturing memory device

    公开(公告)号:US12114514B2

    公开(公告)日:2024-10-08

    申请号:US18519230

    申请日:2023-11-27

    CPC classification number: H10B63/845 H10B61/22 H10B63/34 H10N50/01 H10N70/066

    Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

    MEMORY DEVICE AND IN-MEMORY SEARCH METHOD THEREOF

    公开(公告)号:US20240221830A1

    公开(公告)日:2024-07-04

    申请号:US18173096

    申请日:2023-02-23

    CPC classification number: G11C15/04 G11C16/0483 G11C16/26

    Abstract: A memory device and an in-memory search method thereof are provided. The memory device includes a first memory cell block, a second memory cell block, at least one search memory cell pair, and a sense amplifier. The search memory cell pair includes a first search memory cell and a second search memory cell. The first search memory cell and the second search memory cell are respectively disposed in the first memory cell block and the second memory cell block. The first search memory cell and the second search memory cell respectively receive a first search voltage and a second search voltage. The first search voltage and the second search voltage are generated according to searched data. The sense amplifier generates a search result according to signals on a first bit line and a second bit line.

    Memory device and data search method for in-memory search

    公开(公告)号:US11955186B2

    公开(公告)日:2024-04-09

    申请号:US17812243

    申请日:2022-07-13

    CPC classification number: G11C16/3404 G11C16/26 G11C16/30 G11C15/04 G11C15/046

    Abstract: A memory device for in-memory search is provided. The memory device includes a plurality of memory cells, and each of the memory cells stores a stored data and receives a search data, including a first transistor and a second transistor. The first transistor has a first threshold voltage and receives a first gate bias. The second transistor is connected to the first transistor, and the second transistor has a second threshold voltage and receives a second gate bias. The stored data is encoded according to the first threshold voltage and the second threshold voltage, and the search data is encoded according to the first gate bias and the second gate bias. There is a mismatch distance between the stored data and the search data. An output current generated by each of the memory cells is related to the mismatch distance.

    Analog content-address memory having approximation matching and operation method thereof

    公开(公告)号:US11875849B2

    公开(公告)日:2024-01-16

    申请号:US17711073

    申请日:2022-04-01

    CPC classification number: G11C15/046

    Abstract: An analog content-address memory (analog CAM) having approximation matching and an operation method thereof are provided. The analog CAM includes an inputting circuit, at least one analog CAM cell and an outputting circuit. The inputting circuit is configured to provide an inputting data. The analog CAM cell is connected to the inputting circuit and receives the inputting data. The analog CAM cell has a mild swing match curve whose highest point corresponds to a stored data. A segment from the highest point of the mild swing match curve to a lowest point of the mild swing match curve corresponds to at least three data values. The outputting circuit is connected to the analog CAM cell and receives a match signal from the analog CAM cell. The outputting circuit outputs a match approximation level according to the match signal.

    Analog content-address memory and operation method thereof

    公开(公告)号:US11657876B2

    公开(公告)日:2023-05-23

    申请号:US17325244

    申请日:2021-05-20

    Abstract: An analog CAM and an operation method thereof are provided. The analog CAM includes a matching line, an analog CAM cell and a sense amplifier. Each of the at least one analog CAM includes a first floating gate device having a N type channel and a second floating gate device having a P type channel. A match range is set through programming the first floating gate device and the second floating gate device. The sense amplifier is connected to the matching line. If an inputting signal is within the match range, a voltage of the matching line is pulled down to be equal to or lower than a predetermined level. The sense amplifier outputs a match result if the voltage of the matching line is pulled down to a predetermined level.

    Ternary content addressable memory and memory cell thereof

    公开(公告)号:US11328775B2

    公开(公告)日:2022-05-10

    申请号:US17065516

    申请日:2020-10-07

    Abstract: A ternary content addressable memory and a memory cell thereof are provided. The ternary content addressable memory cell includes a first transistor and a second transistor. The first transistor has a gate to receive a selection signal. A first end of the first transistor is coupled to a match line. A second end of the first transistor is coupled to a source line. The second transistor has a gate to receive an inverted selection signal. A first end of the second transistor is coupled to the match line. A second end of the second transistor is coupled to the source line. The first and second transistors have charge storage structures.

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