公开(公告)号：US08618964B2

公开(公告)日：2013-12-31

申请号：US13207887

申请日：2011-08-11

申请人： Afshin Momtaz ,  Namik Kocaman ,  Bharath Raghavan

发明人： Afshin Momtaz ,  Namik Kocaman ,  Bharath Raghavan

IPC分类号： H03M1/06

CPC分类号： H03F3/45475 ,  H03F3/45183 ,  H03F2203/45686

摘要： According to one general aspect, a distributed threshold adjuster (DTA) may be interspersed between stages of a multistage amplifier to adjust the DC voltage of an input signal. The DTA may include an input signal terminal configured to receive the input signal. The DTA may also include a plurality of current sources configured to produce an adjustment current signal whose amperage is configured to be increased or decreased by fixed steps in order to adjust the DC voltage of the input signal. The DTA may include a control unit configured to selectively turn on or off the individual current sources of the plurality of current sources to select the amperage of the adjustment current signal. The DTA may further include an output terminal configured to produce an output signal, comprising a combination of the input signal and the adjustment current signal, to a stage of a multistage amplifier.

摘要翻译： 根据一个一般方面，分布式阈值调节器（DTA）可以分散在多级放大器的级之间，以调节输入信号的直流电压。 DTA可以包括被配置为接收输入信号的输入信号端子。 DTA还可以包括多个电流源，其被配置为产生调节电流信号，其安培数被配置为通过固定步长增加或减小，以便调节输入信号的直流电压。 DTA可以包括控制单元，其被配置为选择性地打开或关闭多个电流源的各个电流源，以选择调节电流信号的电流强度。 DTA还可以包括输出端子，其被配置为产生包括输入信号和调整电流信号的组合的输出信号到多级放大器的级。

公开(公告)号：US20110074610A1

公开(公告)日：2011-03-31

申请号：US12567841

申请日：2009-09-28

申请人： Adesh Garg ,  Afshin Momtaz ,  Namik Kocaman ,  Delong Cui

发明人： Adesh Garg ,  Afshin Momtaz ,  Namik Kocaman ,  Delong Cui

IPC分类号： H03M7/12

CPC分类号： H04L25/0276 ,  H03M5/04 ,  H04L25/0274 ,  H04L25/0282 ,  H04L25/0284

摘要： A gating logic receives a non-return-to-zero (NRZ) input signal and couples the NRZ input signal as an NRZ output signal when operating in a NRZ mode of operation and converts the NRZ input signal to a return-to-zero (RZ) output signal when operating in a RZ mode of operation. A circuit coupled to the gating logic receives a clock signal and couples the clock signal to the gating logic to convert the NRZ input signal to the RZ output signal in the RZ mode of operation. In the NRZ mode of operation, the circuit decouples the clock signal and places a predetermined signal state at the gating logic to pass through the NRZ input signal as the NRZ output signal. The circuit receives a select signal to select between the NRZ and RZ modes of operation and the NRZ and RZ modes are obtained by controlling the clock signal to the gating logic.

摘要翻译： 门控逻辑接收非归零（NRZ）输入信号，并且在NRZ工作模式下将NRZ输入信号耦合为NRZ输出信号，并将NRZ输入信号转换为零（ RZ）输出信号。 耦合到门控逻辑的电路接收时钟信号并将时钟信号耦合到门控逻辑，以将RZ输入信号转换为RZ工作模式的RZ输出信号。 在NRZ工作模式下，电路解耦时钟信号，并在门控逻辑上放置预定的信号状态，以通过NRZ输入信号作为NRZ输出信号。 该电路接收选择信号以在NRZ和RZ工作模式之间进行选择，并通过控制门控逻辑的时钟信号获得NRZ和RZ模式。

公开(公告)号：US07324548B2

公开(公告)日：2008-01-29

申请号：US10355472

申请日：2003-01-31

申请人： Vikram Natarajan ,  Kang Xiao ,  Mario Caresosa ,  Jay Proano ,  David Chung ,  Afshin Momtaz ,  Randy Stolaruk ,  Xin Wang ,  Namik Kocaman

发明人： Vikram Natarajan ,  Kang Xiao ,  Mario Caresosa ,  Jay Proano ,  David Chung ,  Afshin Momtaz ,  Randy Stolaruk ,  Xin Wang ,  Namik Kocaman

IPC分类号： H04J3/16 ,  H04J3/22 ,  H04J14/00 ,  H04B10/00

CPC分类号： H04Q11/0478 ,  H04J3/04 ,  H04J3/0685 ,  H04J3/1611 ,  H04J2203/0046 ,  H04J2203/0067 ,  H04J2203/0082 ,  H04J2203/0089 ,  Y10S370/907

摘要： Present herein is a multirate transceiver wherein data can be received at a first data rate and transmitted at a second data rate. The transceiver device comprises a first interface for receiving data at one data rate a mapper that can map data from a first rate to the second rate, and a second interface for transmitting the data at the second data rate.

摘要翻译： 本发明是一种多速率收发器，其中可以以第一数据速率接收数据并以第二数据速率发送数据。 收发器装置包括用于以一个数据速率接收能够将数据从第一速率映射到第二速率的映射器的数据的第一接口和用于以第二数据速率发送数据的第二接口。

公开(公告)号：US06927606B2

公开(公告)日：2005-08-09

申请号：US10267054

申请日：2002-10-07

申请人： Namik Kocaman

发明人： Namik Kocaman

IPC分类号： H03K19/017 ,  H03K19/0185 ,  H03K19/094 ,  H03K3/00

CPC分类号： H03K19/018514 ,  H03K19/01707 ,  H03K19/09429

摘要： Method and circuitry for converting a differential logic signal to a single-ended logic signal eliminate slower PMOS transistors and speed up the conversion process. In specific embodiments differential logic signals of the type employed in, for example, current-controlled complementary metal-oxide-semiconductor (C3MOS) logic are converted to single-ended rail-to-rail CMOS logic levels using a differential pair of NMOS transistors with resistors as load devices and an NMOS current source transistor that provides dynamically adjusted tail current.

摘要翻译： 用于将差分逻辑信号转换为单端逻辑信号的方法和电路消除了较慢的PMOS晶体管并加速了转换过程。 在具体实施例中，在例如电流控制的互补金属氧化物半导体（C3MOS）逻辑中使用的类型的差分逻辑信号被转换为单端轨至轨CMOS逻辑电平，使用具有 电阻作为负载器件和NMOS电流源晶体管，提供动态调整的尾电流。

公开(公告)号：US07560986B2

公开(公告)日：2009-07-14

申请号：US11731481

申请日：2007-03-30

申请人： Namik Kocaman

发明人： Namik Kocaman

IPC分类号： H03F3/45

CPC分类号： H03G3/3084 ,  H03G1/0088

摘要： A fine granularity, wide-range variable gain amplifier (“VGA”) comprises an attenuator, a high gain signal path, a low gain signal path and a gain adjustment control to adjust a gain of the VGA, wherein the gain adjustment control is configured to cause a selective activation of at least a portion of the low gain signal path or the high gain signal path to achieve a desired overall gain.

摘要翻译： 精细粒度的宽范围可变增益放大器（“VGA”）包括衰减器，高增益信号路径，低增益信号路径和增益调整控制以调整VGA的增益，其中增益调整控制被配置 以引起低增益信号路径或高增益信号路径的至少一部分的选择性激活以实现期望的总增益。

公开(公告)号：US07391838B2

公开(公告)日：2008-06-24

申请号：US10444023

申请日：2003-05-22

申请人： Mario Caresosa ,  Namik Kocaman

发明人： Mario Caresosa ,  Namik Kocaman

IPC分类号： H03D3/24

CPC分类号： H04L7/033 ,  H03L7/099 ,  H03L7/0998 ,  H03L7/18 ,  H04J3/04 ,  H04J3/0685 ,  H04J2203/0089

摘要： A phase lock loop comprising a plurality of voltage controlled oscillators is presented herein. The phase lock loop can provide a wide range of output frequencies with low jitter. Additionally, the phase lock loop can be incorporated into a clock multiplier unit and a clock and data recovery unit.

摘要翻译： 本文给出了包括多个压控振荡器的锁相环。 锁相环可以提供宽范围的低抖动输出频率。 此外，锁相环可以并入时钟倍增器单元和时钟和数据恢复单元中。

公开(公告)号：US09136904B2

公开(公告)日：2015-09-15

申请号：US13567721

申请日：2012-08-06

申请人： Tamer Ali ,  Ali Nazemi ,  Namik Kocaman

发明人： Tamer Ali ,  Ali Nazemi ,  Namik Kocaman

IPC分类号： H04L25/06 ,  H04B3/04 ,  H04B3/14 ,  H04L25/03 ,  H04L27/00

CPC分类号： H04B3/04 ,  H04B3/14 ,  H04L25/03878 ,  H04L25/063 ,  H04L27/0002

摘要： Embodiments of the present disclosure enable bandwidth extension of receiver front-end circuits without the use of inductors. As a result, significantly smaller and cheaper receiver implementations are made possible. In an embodiment, bandwidth extension is achieved by virtue of very small floating capacitors that are coupled around amplifier stages of the receiver front-end circuit. Each of the capacitors is configured to generate a negative capacitance for the preceding stage (e.g., equalizer or amplifier), thus extending the bandwidth of the preceding stage. A capacitively-degenerated cross-coupled transistor pair allows bandwidth extension for the final (e.g., amplifier) stage. Embodiments further enable DC offset compensation with the use of a digital feedback loop. The feedback loop can thus be turned on/off as needed, reducing power consumption.

摘要翻译： 本公开的实施例使得接收机前端电路的带宽扩展不使用电感器。 因此，可以实现显着更小和更便宜的接收机实现。 在一个实施例中，通过在接收器前端电路的放大器级耦合的非常小的浮动电容器来实现带宽扩展。 每个电容器被配置为为前一级（例如，均衡器或放大器）产生负电容，从而延长前一级的带宽。 电容退化的交叉耦合晶体管对允许最终（例如，放大器）级的带宽扩展。 实施例还使用数字反馈回路实现DC偏移补偿。 因此，可以根据需要打开/关闭反馈回路，从而降低功耗。

公开(公告)号：US20140036982A1

公开(公告)日：2014-02-06

申请号：US13567721

申请日：2012-08-06

申请人： Tamer ALI ,  Ali Nazemi ,  Namik Kocaman

发明人： Tamer ALI ,  Ali Nazemi ,  Namik Kocaman

IPC分类号： H04L27/01

CPC分类号： H04B3/04 ,  H04B3/14 ,  H04L25/03878 ,  H04L25/063 ,  H04L27/0002

摘要： Embodiments of the present disclosure enable bandwidth extension of receiver front-end circuits without the use of inductors. As a result, significantly smaller and cheaper receiver implementations are made possible. In an embodiment, bandwidth extension is achieved by virtue of very small floating capacitors that are coupled around amplifier stages of the receiver front-end circuit. Each of the capacitors is configured to generate a negative capacitance for the preceding stage (e.g., equalizer or amplifier), thus extending the bandwidth of the preceding stage. A capacitively-degenerated cross-coupled transistor pair allows bandwidth extension for the final (e.g., amplifier) stage. Embodiments further enable DC offset compensation with the use of a digital feedback loop. The feedback loop can thus be turned on/off as needed, reducing power consumption.

摘要翻译： 本公开的实施例使得接收机前端电路的带宽扩展不使用电感器。 因此，可以实现显着更小和更便宜的接收机实现。 在一个实施例中，通过在接收器前端电路的放大器级耦合的非常小的浮动电容器来实现带宽扩展。 每个电容器被配置为为前一级（例如，均衡器或放大器）产生负电容，从而延长前一级的带宽。 电容退化的交叉耦合晶体管对允许最终（例如，放大器）级的带宽扩展。 实施例还使用数字反馈回路实现DC偏移补偿。 因此，可以根据需要打开/关闭反馈回路，从而降低功耗。

公开(公告)号：US07496133B2

公开(公告)日：2009-02-24

申请号：US10299892

申请日：2002-11-19

申请人： Ichiro Fujimori ,  Mario Caresosa ,  Namik Kocaman

发明人： Ichiro Fujimori ,  Mario Caresosa ,  Namik Kocaman

IPC分类号： H04B1/38

CPC分类号： H03H11/1291

摘要： An apparatus and method are disclosed to aid a transceiver chip, in a wide-band serial data communications system, in receiving data at multiple data rates. A multi-rate filter within the transceiver chip is implemented as at least one adjustable-rate filter stage and a limiting stage. The at least one adjustable-rate filter stage is used to generate a filtered serial data signal from a received serial data signal. The limiter stage generates a full-swing serial data signal from the filtered serial data signal. A bandwidth of the at least one adjustable-rate filter stage is adjustable in order to receive serial data signals at multiple data rates. The bandwidth of the multi-rate filter within the transceiver chip is selectable by the user of the wide-band communication system.

摘要翻译： 公开了一种用于帮助宽带串行数据通信系统中的收发器芯片以多个数据速率接收数据的装置和方法。 收发器芯片内的多速率滤波器被实现为至少一个可调速率滤波器级和限制级。 所述至少一个可调速率滤波器级用于从接收到的串行数据信号产生滤波的串行数据信号。 限幅器级从滤波后的串行数据信号产生全方位串行数据信号。 至少一个可调速率滤波器级的带宽是可调节的，以便以多个数据速率接收串行数据信号。 收发器芯片内的多速率滤波器的带宽可由宽带通信系统的用户选择。

公开(公告)号：US20080238542A1

公开(公告)日：2008-10-02

申请号：US11731481

申请日：2007-03-30

申请人： Namik Kocaman

发明人： Namik Kocaman

IPC分类号： H03G3/20

CPC分类号： H03G3/3084 ,  H03G1/0088

摘要： A fine granularity, wide-range variable gain amplifier (“VGA”) comprises an attenuator, a high gain signal path, a low gain signal path and a gain adjustment control to adjust a gain of the VGA, wherein the gain adjustment control is configured to cause a selective activation of at least a portion of the low gain signal path or the high gain signal path to achieve a desired overall gain.

摘要翻译： 精细粒度的宽范围可变增益放大器（“VGA”）包括衰减器，高增益信号路径，低增益信号路径和增益调整控制以调整VGA的增益，其中增益调整控制被配置 以引起低增益信号路径或高增益信号路径的至少一部分的选择性激活以实现期望的总增益。