公开(公告)号：US08094056B2

公开(公告)日：2012-01-10

申请号：US12283853

申请日：2008-09-15

申请人： Ali Nazemi ,  Georgios Asmanis ,  German Cesar Augusto Luna ,  Mahyar Kargar ,  Carl Grace ,  Sumant Ramprasad

发明人： Ali Nazemi ,  Georgios Asmanis ,  German Cesar Augusto Luna ,  Mahyar Kargar ,  Carl Grace ,  Sumant Ramprasad

IPC分类号： H03M1/20

CPC分类号： H03M1/1042 ,  H03M1/1215 ,  H03M1/44

摘要： A lookahead pipelined ADC architecture uses open-loop residue amplifiers with calibration. This approach is able to achieve a high-speed, high-accuracy ADC with reduced power consumption. In one aspect, an ADC pipeline unit includes a plurality of lookahead pipeline stages (i.e., an ADC lookahead pipeline) coupled to a calibration unit. The ADC lookahead pipeline uses open-loop residue amplifiers. The calibration unit compensates for non-linearity in the open-loop amplifiers.

摘要翻译： 先进的流水线ADC架构使用开环残余放大器进行校准。 这种方法能够实现具有降低功耗的高速，高精度ADC。 在一个方面，ADC流水线单元包括耦合到校准单元的多个先行流水线级（即，ADC先行流水线）。 ADC前端管道使用开环残留放大器。 校准单元补偿开环放大器中的非线性。

公开(公告)号：US08664973B2

公开(公告)日：2014-03-04

申请号：US13567682

申请日：2012-08-06

申请人： Tamer Ali ,  Ali Nazemi

发明人： Tamer Ali ,  Ali Nazemi

IPC分类号： H03K17/16 ,  H03K19/003 ,  H03L5/00

CPC分类号： H04L25/0298 ,  H04L25/0278

摘要： Embodiments of the present disclosure provide input termination circuits that overcome the deficiencies of conventional designs. Specifically, embodiments eliminate large-on chip bypass capacitors that are commonly used for common mode termination, and instead use an active capacitor-multiplier (C-multiplier) circuit at the common mode node. The C-multiplier circuit mimics a large capacitor at high frequency. By eliminating large on-chip bypass capacitors, the IC design (e.g., receiver) is reduced in size, without affecting common mode return loss performance. Embodiments may be used with any applications that require input termination, and particularly with differential applications that require common mode termination.

摘要翻译： 本公开的实施例提供了克服常规设计的缺陷的输入终端电路。 具体地，实施例消除了通常用于共模终止的大片上旁路电容器，而是在共模节点处使用有源电容乘法器（C乘法器）电路。 C倍频器电路以高频模拟大电容器。 通过消除大的片上旁路电容器，IC设计（例如，接收器）的尺寸减小，而不影响共模回波损耗性能。 实施例可以用于需要输入终止的任何应用，特别是需要共模终止的差分应用。

公开(公告)号：US20140035696A1

公开(公告)日：2014-02-06

申请号：US13567682

申请日：2012-08-06

申请人： Tamer ALI ,  Ali Nazemi

发明人： Tamer ALI ,  Ali Nazemi

IPC分类号： H03H7/38

CPC分类号： H04L25/0298 ,  H04L25/0278

摘要： Embodiments of the present disclosure provide input termination circuits that overcome the deficiencies of conventional designs. Specifically, embodiments eliminate large-on chip bypass capacitors that are commonly used for common mode termination, and instead use an active capacitor-multiplier (C-multiplier) circuit at the common mode node. The C-multiplier circuit mimics a large capacitor at high frequency. By eliminating large on-chip bypass capacitors, the IC design (e.g., receiver) is reduced in size, without affecting common mode return loss performance. Embodiments may be used with any applications that require input termination, and particularly with differential applications that require common mode termination.

摘要翻译： 本公开的实施例提供了克服常规设计的缺陷的输入终端电路。 具体地，实施例消除了通常用于共模终止的大片上旁路电容器，而是在共模节点处使用有源电容乘法器（C乘法器）电路。 C倍频器电路以高频模拟大电容器。 通过消除大的片上旁路电容器，IC设计（例如，接收器）的尺寸减小，而不影响共模回波损耗性能。 实施例可以用于需要输入终止的任何应用，特别是需要共模终止的差分应用。

公开(公告)号：US20130076394A1

公开(公告)日：2013-03-28

申请号：US13242643

申请日：2011-09-23

申请人： Burak Catli ,  Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Ullas Singh ,  Jun Cao ,  Afshin Momtaz

发明人： Burak Catli ,  Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Ullas Singh ,  Jun Cao ,  Afshin Momtaz

IPC分类号： H03K19/094 ,  H03K19/0175

CPC分类号： H03K19/0013 ,  H03K19/018521

摘要： An apparatus is disclosed for converting signals from one digital integrated circuit family to be compatible with another digital integrated circuit family. The apparatus includes a primary interface and a secondary interface to convert a differential output signal from one digital integrated circuit family for use as an input signal by another digital integrated circuit family. The primary and secondary interfaces include gain stages that are configurable to provide rail to rail voltage swings and are characterized as having single pole architectures. The secondary interface may be unterminated such that a substantially equal load is presented to both components of the differential output signal.

摘要翻译： 公开了用于将来自一个数字集成电路系列的信号转换为与另一数字集成电路系列兼容的装置。 该装置包括主接口和次级接口，用于转换来自一个数字集成电路系列的差分输出信号，以用作另一数字集成电路系列的输入信号。 主接口和辅助接口包括可配置为提供轨至轨电压摆幅的增益级，并且其特征在于具有单极架构。 次级接口可以是未端接的，使得对差分输出信号的两个分量提供基本上相等的负载。

公开(公告)号：US07808417B2

公开(公告)日：2010-10-05

申请号：US12283788

申请日：2008-09-15

申请人： Ali Nazemi

发明人： Ali Nazemi

IPC分类号： H03M1/38

CPC分类号： H03M1/44

摘要： A lookahead pipelined ADC architecture uses open-loop residue amplifiers with calibration. This approach is able to achieve a high-speed, high-accuracy ADC with reduced power consumption. In one aspect, an ADC pipeline unit includes a plurality of lookahead pipeline stages (i.e., an ADC lookahead pipeline) coupled to a calibration unit. The ADC lookahead pipeline uses open-loop residue amplifiers. The calibration unit compensates for non-linearity in the open-loop amplifiers.

摘要翻译： 先进的流水线ADC架构使用开环残余放大器进行校准。 这种方法能够实现具有降低功耗的高速，高精度ADC。 在一个方面，ADC流水线单元包括耦合到校准单元的多个先行流水线级（即，ADC先行流水线）。 ADC前端管道使用开环残留放大器。 校准单元补偿开环放大器中的非线性。

公开(公告)号：US09136904B2

公开(公告)日：2015-09-15

申请号：US13567721

申请日：2012-08-06

申请人： Tamer Ali ,  Ali Nazemi ,  Namik Kocaman

发明人： Tamer Ali ,  Ali Nazemi ,  Namik Kocaman

IPC分类号： H04L25/06 ,  H04B3/04 ,  H04B3/14 ,  H04L25/03 ,  H04L27/00

CPC分类号： H04B3/04 ,  H04B3/14 ,  H04L25/03878 ,  H04L25/063 ,  H04L27/0002

摘要： Embodiments of the present disclosure enable bandwidth extension of receiver front-end circuits without the use of inductors. As a result, significantly smaller and cheaper receiver implementations are made possible. In an embodiment, bandwidth extension is achieved by virtue of very small floating capacitors that are coupled around amplifier stages of the receiver front-end circuit. Each of the capacitors is configured to generate a negative capacitance for the preceding stage (e.g., equalizer or amplifier), thus extending the bandwidth of the preceding stage. A capacitively-degenerated cross-coupled transistor pair allows bandwidth extension for the final (e.g., amplifier) stage. Embodiments further enable DC offset compensation with the use of a digital feedback loop. The feedback loop can thus be turned on/off as needed, reducing power consumption.

摘要翻译： 本公开的实施例使得接收机前端电路的带宽扩展不使用电感器。 因此，可以实现显着更小和更便宜的接收机实现。 在一个实施例中，通过在接收器前端电路的放大器级耦合的非常小的浮动电容器来实现带宽扩展。 每个电容器被配置为为前一级（例如，均衡器或放大器）产生负电容，从而延长前一级的带宽。 电容退化的交叉耦合晶体管对允许最终（例如，放大器）级的带宽扩展。 实施例还使用数字反馈回路实现DC偏移补偿。 因此，可以根据需要打开/关闭反馈回路，从而降低功耗。

公开(公告)号：US20140036982A1

公开(公告)日：2014-02-06

申请号：US13567721

申请日：2012-08-06

申请人： Tamer ALI ,  Ali Nazemi ,  Namik Kocaman

发明人： Tamer ALI ,  Ali Nazemi ,  Namik Kocaman

IPC分类号： H04L27/01

CPC分类号： H04B3/04 ,  H04B3/14 ,  H04L25/03878 ,  H04L25/063 ,  H04L27/0002

摘要： Embodiments of the present disclosure enable bandwidth extension of receiver front-end circuits without the use of inductors. As a result, significantly smaller and cheaper receiver implementations are made possible. In an embodiment, bandwidth extension is achieved by virtue of very small floating capacitors that are coupled around amplifier stages of the receiver front-end circuit. Each of the capacitors is configured to generate a negative capacitance for the preceding stage (e.g., equalizer or amplifier), thus extending the bandwidth of the preceding stage. A capacitively-degenerated cross-coupled transistor pair allows bandwidth extension for the final (e.g., amplifier) stage. Embodiments further enable DC offset compensation with the use of a digital feedback loop. The feedback loop can thus be turned on/off as needed, reducing power consumption.

摘要翻译： 本公开的实施例使得接收机前端电路的带宽扩展不使用电感器。 因此，可以实现显着更小和更便宜的接收机实现。 在一个实施例中，通过在接收器前端电路的放大器级耦合的非常小的浮动电容器来实现带宽扩展。 每个电容器被配置为为前一级（例如，均衡器或放大器）产生负电容，从而延长前一级的带宽。 电容退化的交叉耦合晶体管对允许最终（例如，放大器）级的带宽扩展。 实施例还使用数字反馈回路实现DC偏移补偿。 因此，可以根据需要打开/关闭反馈回路，从而降低功耗。

公开(公告)号：US08618835B2

公开(公告)日：2013-12-31

申请号：US13242643

申请日：2011-09-23

申请人： Burak Catli ,  Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Ullas Singh ,  Jun Cao ,  Afshin Momtaz

发明人： Burak Catli ,  Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Ullas Singh ,  Jun Cao ,  Afshin Momtaz

IPC分类号： H03K19/0175

CPC分类号： H03K19/0013 ,  H03K19/018521

摘要： An apparatus is disclosed for converting signals from one digital integrated circuit family to be compatible with another digital integrated circuit family. The apparatus includes a primary interface and a secondary interface to convert a differential output signal from one digital integrated circuit family for use as an input signal by another digital integrated circuit family. The primary and secondary interfaces include gain stages that are configurable to provide rail to rail voltage swings and are characterized as having single pole architectures. The secondary interface may be unterminated such that a substantially equal load is presented to both components of the differential output signal.

摘要翻译： 公开了用于将来自一个数字集成电路系列的信号转换为与另一数字集成电路系列兼容的装置。 该装置包括主接口和辅助接口，用于转换来自一个数字集成电路系列的差分输出信号，以用作另一数字集成电路系列的输入信号。 主接口和辅助接口包括可配置为提供轨至轨电压摆幅的增益级，并且其特征在于具有单极架构。 次级接口可以是未端接的，使得对差分输出信号的两个分量提供基本上相等的负载。

公开(公告)号：US20090243907A1

公开(公告)日：2009-10-01

申请号：US12283853

申请日：2008-09-15

申请人： Ali Nazemi ,  Georgios Asmanis ,  German Luna ,  Mahyar Kargar ,  Carl Grace ,  Sumant Ramprasad

发明人： Ali Nazemi ,  Georgios Asmanis ,  German Luna ,  Mahyar Kargar ,  Carl Grace ,  Sumant Ramprasad

IPC分类号： H03M1/38

CPC分类号： H03M1/1042 ,  H03M1/1215 ,  H03M1/44

摘要： A lookahead pipelined ADC architecture uses open-loop residue amplifiers with calibration. This approach is able to achieve a high-speed, high-accuracy ADC with reduced power consumption. In one aspect, an ADC pipeline unit includes a plurality of lookahead pipeline stages (i.e., an ADC lookahead pipeline) coupled to a calibration unit. The ADC lookahead pipeline uses open-loop residue amplifiers. The calibration unit compensates for non-linearity in the open-loop amplifiers.

摘要翻译： 先进的流水线ADC架构使用开环残余放大器进行校准。 这种方法能够实现具有降低功耗的高速，高精度ADC。 在一个方面，ADC流水线单元包括耦合到校准单元的多个先行流水线级（即，ADC先行流水线）。 ADC前端管道使用开环残留放大器。 校准单元补偿开环放大器中的非线性。

公开(公告)号：US20090096647A1

公开(公告)日：2009-04-16

申请号：US12283788

申请日：2008-09-15

申请人： Ali Nazemi

发明人： Ali Nazemi

IPC分类号： H03M1/00 ,  H03M1/12

CPC分类号： H03M1/44

摘要： A lookahead pipelined ADC architecture uses open-loop residue amplifiers with calibration. This approach is able to achieve a high-speed, high-accuracy ADC with reduced power consumption. In one aspect, an ADC pipeline unit includes a plurality of lookahead pipeline stages (i.e., an ADC lookahead pipeline) coupled to a calibration unit. The ADC lookahead pipeline uses open-loop residue amplifiers. The calibration unit compensates for non-linearity in the open-loop amplifiers.