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    Data processing system for controlling operation of a sense amplifier in a cache
    21.
    发明授权
    Data processing system for controlling operation of a sense amplifier in a cache 失效
    用于控制缓存中的读出放大器的操作的数据处理系统

    公开(公告)号：US6016534A

    公开(公告)日：2000-01-18

    申请号：US887825

    申请日：1997-07-30

    申请人： Manoj Kumar ,  Huy Van Pham

    发明人： Manoj Kumar ,  Huy Van Pham

    IPC分类号： G11C11/419 ,  G11C15/04 ,  G06F13/00 ,  G11C11/413

    CPC分类号： G11C11/419 ,  G11C15/04

    摘要： A cache memory device having circuitry for controlling operation of a sense amplifier for accessing an array in the data processing system including a cache memory device includes circuitry for enabling the sense amplifier when there is a hit in the array as a result of a read request and disables the sense amplifier when there is a miss in the array as a result of the read request. The cache memory device may receives an address associated with the read request, and compares the address to addresses associated with entries in the array, wherein a hit results when the received address matches at least one of the addresses associated with the entries in the array, and wherein a miss results when the received address does not match at least one of the addresses associated with the entries in the array. The address associated with the read request and the addresses associated with entries in the array are effective addresses. The cache memory device may enable the sense amp only when the array is being accessed by the read request, and only after an entire address associated with the read request has been received.

    摘要翻译： 一种具有用于控制读取放大器的操作的电路的高速缓冲存储器件，该读出放大器用于访问数据处理系统中包括高速缓存存储器件的阵列，该电路包括用于当由于读取请求而在阵列中存在命中时能够使读出放大器工作的电路， 由于读取请求，当数组中存在缺失时，禁用读出放大器。 高速缓冲存储器设备可以接收与读取请求相关联的地址，并且将地址与与阵列中的条目相关联的地址进行比较，其中当接收到的地址匹配与阵列中的条目相关联的至少一个地址时， 并且其中当接收到的地址与与阵列中的条目相关联的至少一个地址不匹配时，导致未命中。 与读取请求相关联的地址和与数组中的条目相关联的地址是有效地址。 高速缓冲存储器装置可以仅在读取请求访问阵列时才能使能感测放大器，并且只有在已经接收到与读取请求相关联的整个地址之后才能使能该读出放大器。

    Write driver and bit line precharge apparatus and method
    22.
    发明授权
    Write driver and bit line precharge apparatus and method 失效
    写入驱动器和位线预充电装置和方法

    公开(公告)号：US5959916A

    公开(公告)日：1999-09-28

    申请号：US19895

    申请日：1998-02-06

    申请人： Manoj Kumar

    发明人： Manoj Kumar

    IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C7/12 ,  G11C11/409 ,  G11C11/417 ,  G11C11/419 ,  G11C13/00 ,  G11C7/00

    CPC分类号： G11C7/1078 ,  G11C11/419 ,  G11C7/12

    摘要： A write driver apparatus (10) is adapted for producing a first data output signal and a second data output signal used in driving data onto a bit line pair (16, 18) associated with an electronic computer memory. The first and second data output signals represent desired data and are produced in response to a data signal, refill signal, and a data propagation clock signal. The data propagation signal is derived from system clock signals. A precharge circuit (12) associated with the write driver (10) operates in response to a precharge clock signal to precharge the bit lines (16, 18) prior to each read or write operation. The precharge clock signal is related to the data propagation signal to ensure that the bit lines (16, 18) are fully precharged prior to a read operation. A keeper circuit (14) associated with the bit lines (16, 18) also helps maintain a desired charge state on the bit lines during a read operation from memory cells (20) connected to the bit lines.

    摘要翻译： 写驱动器装置（10）适用于产生用于将数据驱动到与电子计算机存储器相关联的位线对（16,18）上的第一数据输出信号和第二数据输出信号。 第一和第二数据输出信号表示期望的数据，并且响应于数据信号，再填充信号和数据传播时钟信号产生。 数据传播信号来源于系统时钟信号。 与写入驱动器（10）相关联的预充电电路（12）响应于预充电时钟信号而工作，以在每次读或写操作之前对位线（16,18）进行预充电。 预充电时钟信号与数据传播信号相关，以确保位线（16,18）在读取操作之前被完全预充电。 与位线（16,18）相关联的保持器电路（14）还有助于在连接到位线的存储器单元（20）的读取操作期间在位线上保持期望的电荷状态。

    Cache memory having a selectable cache-line replacement scheme using cache-line registers in a ring configuration with a token indicator
    23.
    发明授权
    Cache memory having a selectable cache-line replacement scheme using cache-line registers in a ring configuration with a token indicator 失效
    具有可选择的高速缓存线替换方案的高速缓存存储器使用具有令牌指示符的环配置中的高速缓存行寄存器

    公开(公告)号：US5937429A

    公开(公告)日：1999-08-10

    申请号：US844550

    申请日：1997-04-21

    申请人： Manoj Kumar ,  Peichun Peter Liu ,  Huy Pham ,  Rajinder Paul Singh

    发明人： Manoj Kumar ,  Peichun Peter Liu ,  Huy Pham ,  Rajinder Paul Singh

    IPC分类号： G06F12/12

    CPC分类号： G06F12/127

    摘要： A cache memory having a selectable cache-line replacement scheme is described. In accordance with a preferred embodiment of the present invention, the cache memory has a number of cache lines, a number of token registers, a token, and a selection circuit. The token registers are connected to each other in a ring configuration. There is an equal number of token registers and cache lines, and each of the token registers is associated with one of the cache lines. The token is utilized to indicate one of the cache lines as a candidate for replacement by the associated token register in which the token settles. The selection circuit is associated with all of the token registers. This selection circuit provides at least two methods of controlling the movement of the token within the ring of the token registers, to be selectable during runtime. Each method of token movement represents a cache-line replacement scheme.

    摘要翻译： 描述了具有可选择的高速缓存线更换方案的高速缓冲存储器。 根据本发明的优选实施例，高速缓冲存储器具有多个高速缓存线，多个令牌寄存器，令牌和选择电路。 令牌寄存器以环形配置相互连接。 存在相等数量的令牌寄存器和高速缓存行，并且每个令牌寄存器与其中一个高速缓存行相关联。 令牌被用于将一个缓存行指示为由令牌结算的相关联的令牌寄存器替换的候选。 选择电路与所有令牌寄存器相关联。 该选择电路提供至少两种方法来控制令牌在令牌寄存器的环内的移动，以便在运行时期间可选择。 令牌移动的每种方法代表高速缓存行替换方案。

    Disk access method for delivering multimedia and video information on demand over wide area networks
    24.
    发明授权
    Disk access method for delivering multimedia and video information on demand over wide area networks 失效
    用于在广域网上按需传送多媒体和视频信息的磁盘访问方法

    公开(公告)号：US5915094A

    公开(公告)日：1999-06-22

    申请号：US866671

    申请日：1997-06-02

    申请人： Jack Lawrence Kouloheris ,  Manoj Kumar

    发明人： Jack Lawrence Kouloheris ,  Manoj Kumar

    IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F13/00 ,  H04H20/76 ,  H04H60/27 ,  H04L12/18 ,  H04N5/765 ,  H04N5/93 ,  H04N7/173 ,  H04N21/2312 ,  H04N21/238 ,  H04N21/262 ,  G06F13/38 ,  G06F15/17

    CPC分类号： H04N21/2326 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0689 ,  H04N7/17336

    摘要： A method and apparatus for delivering multimedia video data from a server (host processor) to a plurality of clients connected to a communications network. More specifically, with this invention, preprocessed video and multimedia data packets are striped across disks in units of fixed playback time, even if such units result in variable length stripes. To deliver multiple video or continuous media streams, the disks in the array are accessed simultaneously so that at any given instance, different disks are accessing the video or multimedia data for different streams. Access to the disks for reading the continuous media files is scheduled periodically, with the period equal to the back time of the stripes. Because each disk read command retrieves data for a fixed play back time, if the first read command for a continuous media stream request can be scheduled to complete on a disk within a playback time, all subsequent read commands are also guaranteed to not interfere with read commands of other streams. Data is delivered directly from the disk array to the communication network by a stream controller without being sent to the host system. Disk storage is utilized efficiently by allocating disk space in units of cylinders and storing the variable size stripes of video in packed format.

    摘要翻译： 一种用于将多媒体视频数据从服务器（主处理器）传送到连接到通信网络的多个客户端的方法和装置。 更具体地说，利用本发明，即使这样的单元导致可变长度的条带，预处理的视频和多媒体数据分组以固定的播放时间为单位在磁盘上条带化。 为了提供多个视频或连续媒体流，阵列中的磁盘被同时访问，使得在任何给定的实例中，不同的磁盘正在访问用于不同流的视频或多媒体数据。 周期性地定期访问用于读取连续媒体文件的磁盘，周期等于条带的后续时间。 由于每个磁盘读取命令检索固定播放时间的数据，如果连续媒体流请求的第一个读取命令可以在播放时间内调度到一个磁盘上完成，所有后续的读取命令也保证不会干扰读取 其他流的命令。 数据通过流控制器直接从磁盘阵列传送到通信网络，而不会发送到主机系统。 通过以圆柱体为单位分配磁盘空间并以压缩格式存储视频的可变大小条带来有效地利用磁盘存储。

    System and method for testing self-timed memory arrays
    25.
    发明授权
    System and method for testing self-timed memory arrays 失效
    用于测试自定时存储器阵列的系统和方法

    公开(公告)号：US5896399A

    公开(公告)日：1999-04-20

    申请号：US763493

    申请日：1996-12-11

    申请人： George McNeil Lattimore ,  Michael Kevin Ciraula ,  Dieter F. Wendel ,  Manoj Kumar ,  Friedrich-Christian Wernicke

    发明人： George McNeil Lattimore ,  Michael Kevin Ciraula ,  Dieter F. Wendel ,  Manoj Kumar ,  Friedrich-Christian Wernicke

    IPC分类号： G11C29/14 ,  G11C29/00

    CPC分类号： G11C29/14

    摘要： The present invention applies a Static Evaluate technique to a memory array in a selective manner that allows some parts of the array to use the technique, and yet keeps the array area and timing unaffected for normal operation. The present invention allows the decode functions of the memory array to become pseudo-static during a first part of a clock cycle. In addition, if a write function is being performed, the write data is also held pseudo-static and is not written until a second part of a clock cycle when all addresses and data have stabilized. The invention can be used for system debug, product bring-up, or burn-in, even if there are non-functional race paths. A system and method of testing and burning in self-timed memory arrays includes a Static Evaluate circuit applied to the decoding function and the writing function of the array, a circuit for holding an address or write data inactive for the first part of a cycle, a circuit for activating the address or write data for the second part of a cycle, and a circuit for ensuring that the array resets correctly.

    摘要翻译： 本发明以选择性方式将静态评估技术应用于存储器阵列，其允许阵列的某些部分使用该技术，并且仍保持阵列区域和定时不受正常操作的影响。 本发明允许存储器阵列的解码功能在时钟周期的第一部分期间变为伪静态。 此外，如果正在执行写入功能，则写入数据也保持为伪静态，并且在所有地址和数据均已稳定时，不会写入时钟周期的第二部分。 即使存在非功能性赛跑路径，本发明也可用于系统调试，产品开机或老化。 在自定时存储器阵列中测试和刻录的系统和方法包括应用于解码功能的静态评估电路和阵列的写入功能，用于保持地址或写入对于循环的第一部分无效的数据的电路， 用于激活用于周期的第二部分的地址或写入数据的电路，以及用于确保阵列正确复位的电路。

    Method and apparatus for building business process applications in terms of its workflows
    26.
    发明授权
    Method and apparatus for building business process applications in terms of its workflows 失效
    根据工作流程构建业务流程应用程序的方法和设备

    公开(公告)号：US5734837A

    公开(公告)日：1998-03-31

    申请号：US182744

    申请日：1994-01-14

    申请人： Pablo A. Flores ,  Rodrigo F. Flores ,  Raul Medina-Mora Icaza ,  Jaime Garza Vasquez ,  John A. McAfee ,  Manoj Kumar ,  Manuel Jasso Nunez ,  Terry Allen Winograd ,  Harry K. T. Wong ,  Roy I. Gift

    发明人： Pablo A. Flores ,  Rodrigo F. Flores ,  Raul Medina-Mora Icaza ,  Jaime Garza Vasquez ,  John A. McAfee ,  Manoj Kumar ,  Manuel Jasso Nunez ,  Terry Allen Winograd ,  Harry K. T. Wong ,  Roy I. Gift

    IPC分类号： G06Q10/06 ,  G06Q10/10 ,  G06F19/00

    CPC分类号： G06Q10/10 ,  G06F8/35 ,  G06F8/36 ,  G06Q10/06311 ,  G06Q10/06316

    摘要： The invention is a method and system which provides consultants, business process analysts, and application developers with a unified tool with which to conduct business process analysis, design, documentation and to generate business process definitions and workflow-enabled applications. The invention may be implemented using a software system which has two functional sets. One is a set of graphical tools that can be used by a developer or business analyst to map out business processes. The second is a set of tools that can be used to document and specify in detail the attributes of each workflow definition, including roles, cycle time, conditions, of satisfaction, cost and value, associated text, forms, application data as well as detail the attributes of links between workflows required to complete a business process map, and to generate a business process definition and a workflow-enabled application. In this manner, the invention provides the capability of performing application generation and generation of business process definitions in a definitions database. The invention also includes a workflow language scripting capability.

    摘要翻译： 本发明是一种方法和系统，它为顾问，业务流程分析师和应用程序开发人员提供统一的工具，用于进行业务流程分析，设计，文档编制以及生成业务流程定义和启用工作流的应用程序。 本发明可以使用具有两个功能组的软件系统来实现。 一个是一组图形工具，可以由开发人员或业务分析人员用来绘制业务流程。 第二个是一组工具，可用于详细记录和指定每个工作流定义的属性，包括角色，周期时间，条件，满意度，成本和价值，相关文本，表单，应用程序数据以及详细信息 完成业务流程映射所需的工作流之间链接的属性，以及生成业务流程定义和启用工作流的应用程序。 以这种方式，本发明提供了在定义数据库中执行应用生成和生成业务流程定义的能力。 本发明还包括工作流语言脚本能力。

    Interacting methods of data extraction
    29.
    发明授权
    Interacting methods of data extraction 有权
    数据提取的交互方法

    公开(公告)号：US08600990B2

    公开(公告)日：2013-12-03

    申请号：US12059811

    申请日：2008-03-31

    申请人： Shane Robert Vermette ,  Vijay Manguluru ,  Manoj Kumar

    发明人： Shane Robert Vermette ,  Vijay Manguluru ,  Manoj Kumar

    IPC分类号： G06F7/00 ,  G06F17/00 ,  G06F17/30

    CPC分类号： G06F17/30362

    摘要： Extraction methods can interact on a common data source using identifiers that correspond to events or other actions. These identifiers can be updated, whenever appropriate, once the corresponding data has been summarized, in order to provide for multiple extraction methods to operate only on the data of interest, and obtain a lock only on the data within the scope of extraction. High water marks, such as identifiers in the sequent, can be used to further designate which data has previously been extracted. Similarly, summarization methods can interact by utilizing corresponding persistent tables in the flows for the methods, but utilizing separate intermediate tables to allow for data transformations and application of various business rules and tuning techniques. The ability to switch between different methods can accommodate business, performance, or other such needs, and can provide for the dynamic extraction and summarization of different volumes of data.

    摘要翻译： 提取方法可以使用与事件或其他操作对应的标识符在公共数据源上进行交互。 一旦相应的数据已被总结，就可以适当地更新这些标识符，以便提供多种提取方法仅对感兴趣的数据进行操作，并且仅在提取范围内的数据上获得锁定。 可以使用诸如序列中的标识符的高水位标记来进一步指定先前已经提取了哪些数据。 类似地，汇总方法可以通过在方法的流中利用相应的持久表进行交互，但是利用单独的中间表来允许数据转换和应用各种业务规则和调优技术。 在不同方法之间切换的能力可以适应业务，性能或其他此类需求，并且可以提供不同数据量的动态提取和汇总。