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21.发明授权Method and apparatus for avoiding locks by speculatively executing critical sections 有权用于通过推测性地执行关键部分来避免锁的方法和装置公开(公告)号：US06862664B2
公开(公告)日：2005-03-01
申请号：US10439911
申请日：2003-05-16
CPC分类号： G06F12/0862 , G06F9/30116 , G06F9/3842 , G06F9/3857 , G06F9/3863 , G06F9/528 , G06F12/0815 , G06F12/0842
摘要： One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.
摘要翻译： 本发明的一个实施例提供一种通过推测性地执行代码的关键部分来有助于避免锁定的系统。 在操作期间，系统允许进程在程序中推测性地执行代码的关键部分而不首先获得与关键部分相关联的锁定。 如果该过程随后完成关键部分而没有遇到来自另一进程的干扰数据访问，则系统进行在推测执行期间所做的更改，并且通过关键部分恢复程序的正常非推测性执行。 否则，如果在执行关键部分期间遇到来自其他进程的干扰数据访问，则系统将丢弃在推测执行期间所做的更改，并尝试重新执行临界部分。
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22.发明授权Reducing temperature and power by instruction throttling at decode stage of processor pipeline in time constant duration steps 有权通过在时间常数持续时间步长的处理器流水线的解码阶段通过指令节流来降低温度和功率公开(公告)号：US08219831B2
公开(公告)日：2012-07-10
申请号：US12361422
申请日：2009-01-28
CPC分类号： G06F9/3867 , G06F1/206 , G06F1/3203 , G06F9/3869 , Y02D10/16
摘要： A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.
摘要翻译： 处理器包括提供节流功率输出信号的装置。 节流电源输出信号用于确定何时逻辑地调节处理器消耗的功率。 处理器中的至少一个核心包括具有解码管道的管线; 以及耦合到所述设备以接收所述输出信号并且耦合到所述解码管的逻辑功率节流单元。 在接收到满足预定标准的功率节流输出信号的逻辑功率节流单元之后，逻辑功率节流单元使得解码管减少在每个处理器周期解码的平均指令数，而不会物理地改变处理器周期或任何处理器供电电压。
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23.发明授权公开(公告)号：US07904664B2
公开(公告)日：2011-03-08
申请号：US11833314
申请日：2007-08-03
IPC分类号： G06F12/14
CPC分类号： G06F12/0862 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3857 , G06F9/467 , G06F12/0815 , G06F12/0842
摘要： One embodiment of the present invention provides a system that selectively monitors load instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a load instruction during transactional execution of a block of instructions, the system determines whether the load instruction is a monitored load instruction or an unmonitored load instruction. If the load instruction is a monitored load instruction, the system performs the load operation, and load-marks a cache line associated with the load instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the load instruction is an unmonitored load instruction, the system performs the load operation without load-marking the cache line.
摘要翻译： 本发明的一个实施例提供了一种系统，其选择性地监视加载指令以支持进程的事务性执行，其中在事务执行期间进行的改变不被提交到处理器的体系结构状态，直到事务执行成功完成。 在执行指令块的事务执行期间遇到加载指令时，系统确定加载指令是监视加载指令还是不受监控的加载指令。 如果加载指令是被监视的加载指令，则系统执行加载操作，并加载标记与加载指令相关联的高速缓存行，以便随后检测到来自另一进程的高速缓存行的干扰数据访问。 如果加载指令是不受监控的加载指令，则系统将执行加载操作，而不加载标记缓存行。
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24.发明授权公开(公告)号：US07634644B2
公开(公告)日：2009-12-15
申请号：US11534125
申请日：2006-09-21
IPC分类号： G06F9/00
CPC分类号： G06F9/3867 , G06F9/3804 , G06F9/3842
摘要： Architectural techniques and implementations that defer enforcement of certain delayed control transfer instruction (DCTI) sequencing constraints or conventions to later stages of an execution pipeline are described. In this way, complexity of a processor pipeline front-end (including fetch sequencing) can be simplified, at least in-part, by fetching instructions generally without regard to such constraints or conventions. Instead, enforcement of such sequencing constraints and/or conventions may be deferred to one or more pipeline stages associated with commitment or retirement of instructions. Higher fetch bandwidth may be achieved in some realizations when, for example, DCTI couples are encountered in an execution sequence.
摘要翻译： 描述将某些延迟控制传输指令（DCTI）排序约束或约定的执行推迟到执行流水线的后期的架构技术和实现。 以这种方式，处理器流水线前端（包括读取排序）的复杂性可以至少部分地通过一般地取指令来简化，而不考虑这些约束或约定。 相反，这种排序约束和/或约定的执行可以推迟到与指令的承诺或退出相关联的一个或多个流水线阶段。 当在执行序列中遇到例如DCTI耦合时，在某些实现中可以实现更高的获取带宽。
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25.发明授权Method for reducing lock manipulation overhead during access to critical code sections 有权在访问关键代码段时减少锁操作开销的方法公开(公告)号：US07269717B2
公开(公告)日：2007-09-11
申请号：US10637166
申请日：2003-08-08
CPC分类号： G06F9/528 , G06F9/3004 , G06F9/30087 , G06F9/30116 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3857 , Y10S707/99953
摘要： One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program, the system commences transactional execution of the block of instructions following the STE instruction. Changes made during this transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes.
摘要翻译： 本发明的一个实施例支持开始事务执行（STE）指令的执行，其指示要在事务上执行的指令块的开始。 在执行程序期间遇到STE指令时，系统开始按照STE指令执行指令块的事务性执行。 在事务执行之前进行的更改不会在事务执行成功完成之前提交到处理器的体系结构状态。
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26.发明授权公开(公告)号：US07269694B2
公开(公告)日：2007-09-11
申请号：US10637168
申请日：2003-08-08
IPC分类号： G06F12/14
CPC分类号： G06F12/0862 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3857 , G06F9/467 , G06F12/0815 , G06F12/0842
摘要： One embodiment of the present invention provides a system that selectively monitors load instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a load instruction during transactional execution of a block of instructions, the system determines whether the load instruction is a monitored load instruction or an unmonitored load instruction. If the load instruction is a monitored load instruction, the system performs the load operation, and load-marks a cache line associated with the load instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the load instruction is an unmonitored load instruction, the system performs the load operation without load-marking the cache line.
摘要翻译： 本发明的一个实施例提供了一种系统，其选择性地监视加载指令以支持进程的事务性执行，其中在事务执行期间进行的改变不被提交到处理器的体系结构状态，直到事务执行成功完成。 在执行指令块的事务执行期间遇到加载指令时，系统确定加载指令是监视加载指令还是不受监控的加载指令。 如果加载指令是被监视的加载指令，则系统执行加载操作，并加载标记与加载指令相关联的高速缓存行，以便随后检测到来自另一进程的高速缓存行的干扰数据访问。 如果加载指令是不受监控的加载指令，则系统将执行加载操作，而不加载标记缓存行。
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27.发明授权Method and apparatus for releasing memory locations during transactional execution 有权在事务执行期间释放内存位置的方法和装置公开(公告)号：US07206903B1
公开(公告)日：2007-04-17
申请号：US10895519
申请日：2004-07-20
IPC分类号： G06F12/00
CPC分类号： G06F12/0842 , G06F9/30087 , G06F9/3834 , G06F9/3859
摘要： One embodiment of the present invention provides a system for releasing a memory location from transactional program execution. The system operates by executing a sequence of instructions during transactional program execution, wherein memory locations involved in the transactional program execution are monitored to detect interfering accesses from other threads, and wherein changes made during transactional execution are not committed until transactional execution completes without encountering an interfering data access from another thread. Upon encountering a release instruction for a memory location during the transactional program execution, the system modifies state information within the processor to release the memory location from monitoring. The system also executes a commit-and-start-new-transaction instruction, wherein the commit-and-start-new-transaction instruction atomically commits the transaction's stores, thereby removing them from the transaction's write set while the transaction's read set remains unaffected.
摘要翻译： 本发明的一个实施例提供了一种用于将存储器位置从事务程序执行释放的系统。 该系统通过在事务性程序执行期间执行指令序列来操作，其中监视涉及事务性程序执行的存储器位置以检测来自其他线程的干扰访问，并且其中在事务执行期间进行的改变不会被提交直到事务执行完成而不遇到 干扰来自另一个线程的数据访问。 在事务性程序执行期间遇到存储器位置的释放指令时，系统修改处理器内的状态信息以从监视释放存储器位置。 该系统还执行commit-and-start-new-transaction指令，其中commit-and-start-new-transaction指令以原子方式提交事务的存储，从而在事务的读取集保持不受影响的情况下将其从事务的写入集中移除。
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28.发明授权Method and apparatus for providing fault-tolerance for temporary results within a CPU 有权在CPU内为临时结果提供容错的方法和装置公开(公告)号：US07124331B2
公开(公告)日：2006-10-17
申请号：US10146102
申请日：2002-05-14
IPC分类号： G06F11/00
CPC分类号： G06F11/1032 , G06F9/3836 , G06F9/3857 , G06F9/3861 , G06F11/1405
摘要： One embodiment of the present invention provides a system that corrects bit errors in temporary results within a central processing unit (CPU). During operation, the system receives a temporary result during execution of an in-flight instruction. Next, the system generates a parity bit for the temporary result, and stores the temporary result and the parity bit in a temporary register within the CPU. Before the temporary result is committed to the architectural state of the CPU, the system checks the temporary result and the parity bit to detect a bit error. If a bit error is detected, the system performs a micro-trap operation to re-execute the instruction that generated the temporary result, thereby regenerating the temporary result. Otherwise, if a bit error is not detected, the system commits the temporary result to the architectural state of the CPU.
摘要翻译： 本发明的一个实施例提供一种在中央处理单元（CPU）内校正临时结果中的位错误的系统。 在运行期间，系统在执行飞行中指令时收到临时结果。 接下来，系统生成用于临时结果的奇偶校验位，并将临时结果和奇偶校验位存储在CPU内的临时寄存器中。 在临时结果提交到CPU的架构状态之前，系统会检查临时结果和奇偶校验位以检测位错误。 如果检测到位错误，则系统执行微陷阱操作以重新执行产生临时结果的指令，从而重新产生临时结果。 否则，如果未检测到位错误，则系统将临时结果提交给CPU的体系结构状态。
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29.发明授权Selectively unmarking load-marked cache lines during transactional program execution 有权在事务性程序执行期间选择性地取消标记加载标记的高速缓存行公开(公告)号：US07089374B2
公开(公告)日：2006-08-08
申请号：US10764412
申请日：2004-01-23
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3863 , G06F9/467 , G06F12/0862
摘要： One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are monitored during transactional execution to detect interfering accesses from other threads. During operation, the system encounters a release instruction during transactional execution of a block of instructions. In response to the release instruction, the system modifies the state of cache lines, which are specially load-marked to indicate they can be released from monitoring, to account for the release instruction being encountered. In doing so, the system can potentially cause the specially load-marked cache lines to become unmarked. In a variation on this embodiment, upon encountering a commit-and-start-new-transaction instruction, the system modifies load-marked cache lines to account for the commit-and-start-new-transaction instruction being encountered. In doing so, the system causes normally load-marked cache lines to become unmarked, while other specially load-marked cache lines may remain load-marked past the commit-and-start-new-transaction instruction.
摘要翻译： 本发明的一个实施例提供了一种系统，其有助于在事务性程序执行期间有选择地取消标记加载标记的高速缓存行，其中在事务执行期间监视负载标记的高速缓存行以检测来自其他线程的干扰访问。 在操作期间，系统在事务处理指令块期间遇到释放指令。 响应于释放指令，系统修改高速缓存行的状态，这些高速缓存行被特别加载标记以指示它们可以从监视释放，以解决遇到的释放指令。 在这样做时，系统可能会导致特别加载标记的高速缓存行变为未标记。 在该实施例的变型中，当遇到提交和启动新事务指令时，系统修改加载标记的高速缓存行以考虑正在遇到的提交和启动新事务指令。 在这样做时，系统会导致正常加载标记的高速缓存行变为未标记，而其他特别加载标记的高速缓存行可能会通过commit-and-start-new-transaction指令保持加载标记。
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公开(公告)号：US06938130B2
公开(公告)日：2005-08-30
申请号：US10737679
申请日：2003-12-15
CPC分类号： G06F12/0862 , G06F9/3004 , G06F9/30087 , G06F9/30105 , G06F9/30116 , G06F9/3834 , G06F9/3836 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F9/467 , G06F12/0815 , G06F12/0842
摘要： One embodiment of the present invention provides a system that facilitates delaying interfering memory accesses from other threads during transactional execution. During transactional execution of a block of instructions, the system receives a request from another thread (or processor) to perform a memory access involving a cache line. If performing the memory access on the cache line will interfere with the transactional execution and if it is possible to delay the memory access, the system delays the memory access and stores copy-back information for the cache line to enable the cache line to be copied back to the requesting thread. At a later time, when the memory access will no longer interfere with the transactional execution, the system performs the memory access and copies the cache line back to the requesting thread.
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