公开(公告)号：US5805435A

公开(公告)日：1998-09-08

申请号：US824958

申请日：1997-03-27

申请人： Luigi Pascucci

发明人： Luigi Pascucci

IPC分类号： H02M3/07 ,  H02M3/18

CPC分类号： H02M3/07

摘要： A device includes a first line at the supply voltage; a second line at the boost voltage; a booster stage; a supply detecting stage connected to the first line and generating a first level signal when the supply voltage exceeds a first predetermined level; a boost detecting stage connected to the second line and generating a second level signal when the boost voltage exceeds a second predetermined level; a regulating stage enabled by the boost detecting stage; and a pump control stage, which generates a regulating enabling signal for the regulating stage in the absence of the first level signal and in the presence of an enabling signal enabling the boost condition. The regulating stage generates a regulating signal in the presence of the second level signal and the regulating enabling signal, when the boost voltage exceeds a third predetermined level; and the pump control stage generates a pump activating signal for the booster stage in the absence of the first level signal and the regulating signal.

摘要翻译： 设备包括在电源电压下的第一线; 在升压电压下的第二行; 增强阶段; 电源检测级连接到第一线，并且当电源电压超过第一预定电平时产生第一电平信号; 升压检测级，连接到第二线，并且当升压电压超过第二预定电平时产生第二电平信号; 由升压检测级使能的调节级; 以及泵控制级，其在没有第一级信号的情况下产生用于调节级的调节使能信号，并且存在能够进行升压状态的使能信号。 当升压电压超过第三预定电平时，调节级在存在第二电平信号和调节使能信号的情况下产生调节信号; 并且在没有第一电平信号和调节信号的情况下，泵控制级产生用于升压级的泵激活信号。

公开(公告)号：US5764570A

公开(公告)日：1998-06-09

申请号：US691796

申请日：1996-08-02

申请人： Luigi Pascucci

发明人： Luigi Pascucci

IPC分类号： G11C16/28 ,  G11C7/00

CPC分类号： G11C16/28

摘要： A reading circuit for a multibit register has a differential stage that is configured as an output latch by one of two control phases required by the circuit after the discrimination phase of a reading cycle a single NOR gate, the output of which is provided with anti-overshoot means, enables the performance of a reading cycle. An input of the differential stage, is connectable to a common sensing line to which all the cells of the register are coupled in an OR configuration, while the other input is connectable to a reference current generator.

摘要翻译： 用于多位寄存器的读取电路具有差分级，其被配置为在读取周期的识别阶段之后电路所需的两个控制相位之一的单个或非门，其输出被提供有反相器 超调意味着能够执行阅读周期。 差分级的输入可连接到公共感测线，寄存器的所有单元以OR配置耦合到该公共感测线，而另一个输入可连接到参考电流发生器。

公开(公告)号：US5734610A

公开(公告)日：1998-03-31

申请号：US690530

申请日：1996-07-31

申请人： Luigi Pascucci

发明人： Luigi Pascucci

IPC分类号： G11C16/26 ,  G11C16/06

CPC分类号： G11C16/26

摘要： A reading circuit includes, for each bit line of a matrix of memory cells, a controllable switching element which can connect the bit line to a voltage source in response to a control signal applied to a control terminal thereof, a detector stage sensitive to the flow of current through the bit line, and a driving stage including two field-effect transistors connected in the inverter configuration with the input of the inverter connected to the bit line and with the output of the inverter connected to the control terminal of the controllable switching element. In order to charge the capacitance associated with the bit line rapidly but without causing oscillatory phenomena, the driving stage includes circuitry for reducing the gain of the feedback loop formed by the inverter and by the controllable switching element.

摘要翻译： 读取电路包括对于存储器单元矩阵的每个位线，可控开关元件，其可响应于施加到其控制端的控制信号而将位线连接到电压源;对流动敏感的检测器级 的电流，以及驱动级，包括以逆变器配置连接的两个场效应晶体管，连接到位线的反相器的输入端连接到反相器的输出端，连接到可控开关元件的控制端子 。 为了快速地对与位线相关的电容进行充电，但不引起振荡现象，驱动级包括用于降低由逆变器和可控开关元件形成的反馈回路的增益的电路。

公开(公告)号：US5731716A

公开(公告)日：1998-03-24

申请号：US592122

申请日：1996-01-26

申请人： Luigi Pascucci

发明人： Luigi Pascucci

IPC分类号： G11C11/56 ,  G11C15/00 ,  G11C15/04 ,  G11C16/04 ,  G11C29/00 ,  G11C29/04 ,  H03K19/177

CPC分类号： G11C29/781 ,  G11C11/56 ,  G11C15/00 ,  G11C16/0441

摘要： A programmable cell and a multibit register composed of a plurality of such cells, specifically for performing a coincidence check between a certain code permanently recorded in the cell or cells and a logic configuration present on a pair or on a plurality of pairs of control lines are disclosed. Each cell has two branches connected in OR configuration to a common sensing line of the cell or of the multibit register. The logic states to be tested for coincidence are applied in a complemented form through a pair of lines to each cell, that is to the two branches of the cell. Each cell, permanently programmed in one or the other of its branches, intrinsically performs a comparison between its permanently programmed logic configuration and the configuration of the complemented control lines associated therewith. A great simplification is achieved in the overall circuitry of a redundance or reconfiguration system.

摘要翻译： 由多个这样的单元组成的可编程单元和多位寄存器，专门用于执行永久记录在单元或单元中的某个代码与存在于一对或多对控制线上的逻辑配置之间的一致性检查， 披露 每个单元有两个分支以OR配置连接到单元或多位寄存器的公共感测线。 通过一对线对每个单元，即单元格的两个分支，以互补的形式应用待测试的逻辑状态。 在其一个或另一个分支中永久编程的每个单元本质地执行其永久编程逻辑配置与与其相关联的补充控制线的配置之间的比较。 在冗余或重新配置系统的整体电路中实现了很大的简化。

公开(公告)号：US5708601A

公开(公告)日：1998-01-13

申请号：US602237

申请日：1996-02-16

申请人： Vernon G. McKenny ,  Luigi Pascucci ,  Marco Maccarrone

发明人： Vernon G. McKenny ,  Luigi Pascucci ,  Marco Maccarrone

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/835

摘要： An apparatus identifies redundancy memory cells that are selected to replace defective memory cells of a memory matrix that communicates with a data bus. A redundancy address register is associated with one of the redundancy memory cells. The redundancy address register stores a default state until it is programmed with an address of one of the defective memory cells. A control circuit generates a test signal during an identification mode. A detect circuit is coupled to the control circuit and to the redundancy address register and generates a default-detect signal in response to the test signal when the redundancy address register contains the default state. A data-bus multiplexer that is coupled to the redundancy-cell selection circuit, the data bus, and the control circuit couples the default detect signal to the data bus in response to the test signal.

摘要翻译： 一种装置识别被选择来替换与数据总线通信的存储器矩阵的有缺陷的存储单元的冗余存储单元。 冗余地址寄存器与冗余存储单元之一相关联。 冗余地址寄存器存储默认状态，直到用一个缺陷存储单元的地址编程为止。 控制电路在识别模式期间产生测试信号。 检测电路耦合到控制电路和冗余地址寄存器，并且当冗余地址寄存器包含默认状态时，响应于测试信号产生默认检测信号。 耦合到冗余单元选择电路，数据总线和控制电路的数据总线复用器响应于测试信号将默认检测信号耦合到数据总线。

公开(公告)号：US5644529A

公开(公告)日：1997-07-01

申请号：US635455

申请日：1996-04-18

申请人： Luigi Pascucci ,  Silvia Padoan

发明人： Luigi Pascucci ,  Silvia Padoan

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C11/40

CPC分类号： G11C29/789 ,  G11C16/12 ,  G11C29/12

摘要： In an integrated circuit for programming a memory cell in a non-volatile memory register which is associated with a memory matrix wherein the non-volatile memory register is used to store a redundancy address, the memory cell has at least one programmable non-volatile memory element having a control electrode and a data electrode and is suitable to store one bit of information. A load circuit associated to the memory element reads the information stored therein. The integrated circuit has switching means connected in series between the data electrode and a respective address signal line of an address signal bus which also supplies a decoding circuitry of the memory matrix. The switching means are controlled by a signal which determines the switching means to electrically connect the data electrode of the memory element to the address signal line when the memory cell of the non-volatile memory register is to be programmed, and to electrically disconnect the data electrode of the memory element from the address signal line when the information stored in the memory element is to be read by the load circuit.

摘要翻译： 在用于对与非易失性存储器寄存器用于存储冗余地址的存储器矩阵相关联的非易失性存储器寄存器中的存储器单元进行编程的集成电路中，存储器单元具有至少一个可编程非易失性存储器 元件具有控制电极和数据电极，并且适合于存储一位信息。 与存储器元件相关联的负载电路读取存储在其中的信息。 集成电路具有串联连接在数据电极和还提供存储器矩阵的解码电路的地址信号总线的相应地址信号线之间的开关装置。 开关装置由确定开关装置的信号控制，当非易失性存储寄存器的存储单元要被编程时，切换装置将存储元件的数据电极电连接到地址信号线，并且电连接数据 当存储在存储元件中的信息要由负载电路读取时，来自地址信号线的存储元件的电极。

公开(公告)号：US5541884A

公开(公告)日：1996-07-30

申请号：US391147

申请日：1995-02-21

申请人： Luigi Pascucci ,  Carla M. Golla ,  Marco Maccarrone ,  Marco Olivo

发明人： Luigi Pascucci ,  Carla M. Golla ,  Marco Maccarrone ,  Marco Olivo

IPC分类号： G11C11/413 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/06 ,  G11C16/32 ,  G11C17/00

CPC分类号： G11C7/02 ,  G11C16/32 ,  G11C7/1006 ,  G11C7/22

摘要： In a nonvolatile memory comprising a data amplifying unit and an output element mutually connected by a connection line, the noise suppressing circuit comprises a network for generating a noise suppressing signal which is synchronized substantially perfectly with a signal controlling data loading from the amplifying unit to the output unit, presents a very short duration, equal to the switching time of the output unit, and freezes the amplifying unit during switching of the output unit to prevent this from altering the data stored in the amplifying unit or internal circuits of the memory. The same signal also blocks an address amplifying unit on the address bus.

摘要翻译： 在包括数据放大单元和通过连接线相互连接的输出元件的非易失性存储器中，噪声抑制电路包括用于产生噪声抑制信号的网络，该噪声抑制信号与控制从放大单元加载到 输出单元呈现相当于输出单元的切换时间的非常短的持续时间，并且在切换输出单元期间使放大单元冻结，以防止其改变存储在放大单元中的数据或存储器的内部电路。 相同的信号也阻塞地址总线上的地址放大单元。

公开(公告)号：US5321317A

公开(公告)日：1994-06-14

申请号：US936857

申请日：1992-08-27

申请人： Luigi Pascucci ,  Marco Olivo

发明人： Luigi Pascucci ,  Marco Olivo

IPC分类号： G06F1/24 ,  H03K17/00 ,  H03K17/22 ,  G05F1/46

CPC分类号： H03K17/223 ,  H03K2217/0036

摘要： A power-on reset circuit, which may be utilized with CMOS integrated circuits, includes first and second series-connected inverters, wherein the output of the second inverter provides a reset signal. A series of switches and a biasing line having two series-connected diodes are integrally arranged with the inverters. Capacitive coupling to ground and the supply voltage is employed to prevent any static current path between supply voltage rails. The circuit provides a short duration reset signal which follows the supply voltage and is insensitive both to rebound signals on the supply voltage rails and to internal and external noise.

摘要翻译： 可以与CMOS集成电路一起使用的上电复位电路包括第一和第二串联连接的反相器，其中第二反相器的输出提供复位信号。 具有两个串联二极管的一系列开关和偏置线与逆变器一体地布置。 采用与地的电容耦合和电源电压来防止电源电压轨之间的任何静态电流路径。 该电路提供短暂的复位信号，该信号跟随电源电压，对电源电压轨上的回弹信号和内部和外部噪声都不敏感。

公开(公告)号：US4933827A

公开(公告)日：1990-06-12

申请号：US376267

申请日：1989-07-06

申请人： Marco Olivo ,  Luigi Pascucci ,  Corrado Villa

发明人： Marco Olivo ,  Luigi Pascucci ,  Corrado Villa

IPC分类号： H01L27/04 ,  G11C5/14 ,  G11C16/30 ,  H01L21/822 ,  H02M3/07

CPC分类号： G11C5/145 ,  G11C16/30 ,  H02M3/073

摘要： The regulation of the output voltage of a voltage multiplier driven by a ring oscillator, an inverter of which is substituted by a NOR gate for providing a terminal through which stopping the oscillation, is effected by controlling the oscillation frequency in function of the current delivered by the voltage multiplier by means of a transistor T1 working as a current generator connected in series with a regulating chain of series-connected diodes by biasing the gate of the transistor with a constant voltage Vref, thus imposing a reference current Iref through the transistor. The voltage signal across the transistor is fed to the input of a first inverter with a preset triggering threshold and the output signal of the inverter is fed through an amplifying and phase-regenerating stage to said terminal for stopping the oscillation of said NOR gate of the ring oscillator. When the discharge current through the regulating chain becomes greater than the imposed current Iref, across the transistor T1 a voltage signal develops which, beyond a certain threshold, determines the switching of the inverter and, through the amplifying and phase-regenerating stage, causes a stop of the oscillation which resumes only when conduction through the regulating chain stops. At steady state the oscillation frequency will result controlled so as to maintain constant the output voltage of the voltage multiplier and to limit the discharge current through the regulating chain thus limiting power consumption.

公开(公告)号：US08824205B2

公开(公告)日：2014-09-02

申请号：US11279385

申请日：2006-04-11

申请人： Luigi Pascucci ,  Paolo Rolandi

发明人： Luigi Pascucci ,  Paolo Rolandi

IPC分类号： G11C5/06 ,  G11C7/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/24 ,  G11C8/14 ,  G11C8/12 ,  G11C7/18 ,  G11C7/12

CPC分类号： G11C16/08 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/24 ,  Y10T29/49002

摘要： A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.