公开(公告)号：US20100211720A1

公开(公告)日：2010-08-19

申请号：US12458511

申请日：2009-07-14

申请人： Sudhir Kumar Satpathy ,  David Theodore Blaauw ,  Trevor Nigel Mudge ,  Dennis Michael Sylvester

发明人： Sudhir Kumar Satpathy ,  David Theodore Blaauw ,  Trevor Nigel Mudge ,  Dennis Michael Sylvester

IPC分类号： G06F13/00 ,  G06F13/36

CPC分类号： G11C7/10

摘要： Crossbar circuitry, and a method of operation of such crossbar circuitry, are provided. The crossbar circuitry has an array of data input paths and data output paths where the data output paths are transverse to the data input paths. At each intersection between a data input path and a data output path, a crossbar cell is provided that comprises a configuration storage circuit programmable to store a routing value, a transmission circuit, and an arbitration circuit. In a transmission mode of operation, the transmission circuit is responsive to the routing value being a first value, indicating that the data input path should be coupled to the data output path, to detect the data input along the data input path, and to output an indication of that data on the data output path at the associated intersection. In an arbitration mode of operation, the arbitration circuitry is operable in the presence of an asserted transmission request from the associated source circuit to operate in combination with the arbitration circuits of other crossbar cells associated with the same data output path to re-use the bit lines of the data output path to detect the presence of multiple asserted transmission requests for the same data output path. In the event of such multiple asserted transmission requests, the arbitration circuitry operates in combination with the other arbitration circuits to implement a predetermined priority scheme to cause the configuration storage circuit of only one crossbar cell associated with the same data output path to have its routing value programmed to the first value, thereby resolving conflict between the multiple asserted transmission requests according to the predetermined priority scheme. Such a construction of crossbar circuitry enables a very efficient resolution of conflicts to be performed, whilst providing a very regular design, with uniform delay across all paths, and which requires significantly less control lines that typical prior art crossbar designs. Such crossbar circuitry is readily scalable to form large crossbars.

公开(公告)号：US08868817B2

公开(公告)日：2014-10-21

申请号：US13438920

申请日：2012-04-04

申请人： Sudhir Kumar Satpathy ,  David Theodore Blaauw ,  Dennis Michael Sylvester ,  Trevor Nigel Mudge

发明人： Sudhir Kumar Satpathy ,  David Theodore Blaauw ,  Dennis Michael Sylvester ,  Trevor Nigel Mudge

IPC分类号： G06F13/00 ,  G11C7/10 ,  G06F13/40 ,  H03K17/693

CPC分类号： G11C7/10 ,  G06F13/4022 ,  G06F2213/0038 ,  G11C7/1012 ,  H03K17/693

摘要： Interconnect circuitry 2 has a plurality of data source circuits 8 connected to respective input paths 4 and a plurality of data destination circuits 10 connected to respective output paths 6. Connection cells 12 provide selective connections between input paths 4 and output paths 6. Arbitration circuitry 26 provides adaptive priority arbitration between overlapping requests received at different input paths. Priority bits 16 within a matrix of priority bit 46 for each output path 10 are used to represent the priority relationships between different input paths which compete for access to that output path 10. Update operations are applied on a per row or per column basis within the matrix to implement update schemes such as least recently granted, most recently granted, round robin, reversal, swap, selective least recently granted, selective most recently granted etc.

摘要翻译： 互连电路2具有连接到相应输入路径4的多个数据源电路8和连接到相应输出路径6的多个数据目的地电路10.连接单元12提供输入路径4和输出路径6之间的选择性连接。仲裁电路26 在不同输入路径上接收的重叠请求之间提供自适应优先级仲裁。 用于每个输出路径10的优先级位46的矩阵内的优先级位16用于表示竞争对该输出路径10的访问的不同输入路径之间的优先级关系。更新操作按照每行或每列进行应用 矩阵来实现更新计划，例如最近最近授予的，最近授予的，轮回，逆转，掉期，最少选择权，最近授予的选择权。

公开(公告)号：US08255610B2

公开(公告)日：2012-08-28

申请号：US13137487

申请日：2011-08-19

申请人： Sudhir Kumar Satpathy ,  David Theodore Blaauw ,  Trevor Nigel Mudge ,  Dennis Michael Sylvester

发明人： Sudhir Kumar Satpathy ,  David Theodore Blaauw ,  Trevor Nigel Mudge ,  Dennis Michael Sylvester

IPC分类号： G06F13/00

CPC分类号： G11C7/10 ,  G11C7/1006 ,  H03K17/693

摘要： Crossbar circuitry has data input and output paths, and at each intersection between a data input and output path, a crossbar cell is provided. A transmission circuit is responsive to a stored routing value to couple a data input path to a selected data output path. Pre-selection circuitry cooperates with the pre-selection circuits of other crossbar cells on the same data output path to use the bit lines of the data output path to compare quality-of-service values associated with multiple asserted transmission requests and to determine a subset thereof which have a highest value of the quality-of-service values. Arbitration circuitry implements a predetermined priority scheme to choose from that subset of requests and to cause the configuration storage circuit of only one crossbar cell associated with the same data output path to have its routing value programmed to the first value, thereby resolving conflict between multiple asserted transmission requests.

公开(公告)号：US07072229B2

公开(公告)日：2006-07-04

申请号：US11150585

申请日：2005-06-13

申请人： Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge ,  Dennis Michael Sylvester ,  Krisztian Flautner

发明人： Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge ,  Dennis Michael Sylvester ,  Krisztian Flautner

IPC分类号： G11C7/00

CPC分类号： G06F9/3869 ,  G06F9/3861 ,  G06F11/141 ,  G11C7/04 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/22 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C2207/2281

摘要： There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to read said data value from said memory to generate a slow read result available after said fast read result has been output for further processing, said slow data reading mechanism being less prone to error in reading said data value than said fast data reading mechanism; a comparator operable to compare said fast read result and said slow read result to detect if said fast read result differs from said slow read result; and error repair logic operable if said comparator detects that said fast read result differs from said slow read result to suppress said further processing using said fast read result, to output said slow read result in place of said fast read result and to restart said further processing based upon said slow read result.

摘要翻译： 提供了一种用于存储数据的存储器，包括：快速数据读取机构，用于从所述存储器读取数据值，以产生从所述存储器输出的快速读取结果用于进一步处理; 缓慢的数据读取机构，用于从所述存储器读取所述数据值，以产生在所述快速读取结果被输出以供进一步处理之后可用的慢速读取结果，所述慢速数据读取机构在读取所述数据值时不太容易出现所述数据值 快速数据读取机制; 比较器，用于比较所述快速读取结果和所述慢速读取结果，以检测所述快速读取结果是否与所述慢速读取结果不同; 如果所述比较器检测到所述快速读取结果不同于所述慢速读取结果以便使用所述快速读取结果抑制所述进一步处理，则输出所述慢速读取结果代替所述快速读取结果并重启所述进一步处理的错误修复逻辑 基于所述慢读取结果。

公开(公告)号：US06944067B2

公开(公告)日：2005-09-13

申请号：US10779809

申请日：2004-02-18

申请人： Trevor Nigel Mudge ,  Todd Michael Austin ,  David Theodore Blaauw ,  Dennis Michael Sylvester ,  Krisztian Flautner

发明人： Trevor Nigel Mudge ,  Todd Michael Austin ,  David Theodore Blaauw ,  Dennis Michael Sylvester ,  Krisztian Flautner

IPC分类号： G06F1/32 ,  G11C7/00

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/3287 ,  G11C2207/2281 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/171

摘要： There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to read said data value from said memory to generate a slow read result available after said fast read result has been output for further processing, said slow data reading mechanism being less prone to error in reading said data value than said fast data reading mechanism a comparator operable to compare said fast read result and said slow read result to detect if said fast read result differs from said slow read result; and error repair logic operable if said comparator detects that said, fast read result differs from said slow read result to suppress said further processing using said fast read result, to output said slow read result in place of said fast read result and to restart said further processing based upon said slow read result.

摘要翻译： 提供了一种用于存储数据的存储器，包括：快速数据读取机构，用于从所述存储器读取数据值，以产生从所述存储器输出的快速读取结果用于进一步处理; 缓慢的数据读取机构，用于从所述存储器读取所述数据值，以产生在所述快速读取结果被输出以供进一步处理之后可用的慢速读取结果，所述慢速数据读取机构在读取所述数据值时不太容易出现所述数据值 快速数据读取机构，比较器，用于比较所述快速读取结果和所述慢速读取结果，以检测所述快速读取结果是否与所述慢速读取结果不同; 如果所述比较器检测到所述快速读取结果与所述慢速读取结果不同，以便使用所述快速读取结果抑制所述进一步处理，则输出所述慢速读取结果代替所述快速读取结果并重新启动所述更多读取结果的错误修复逻辑 基于所述慢读取结果进行处理。

公开(公告)号：US08650470B2

公开(公告)日：2014-02-11

申请号：US12926084

申请日：2010-10-25

申请人： Krisztian Flautner ,  Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge ,  David Bull

发明人： Krisztian Flautner ,  Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge ,  David Bull

IPC分类号： G06F11/00

CPC分类号： G06F11/0793 ,  G06F11/00 ,  G06F11/0706 ,  G06F11/0736 ,  G06F11/0754 ,  G06F11/0757 ,  G06F11/079 ,  G06F11/1402 ,  G06F11/1604

摘要： An integrated circuit includes one or more portions having error detection and error correction circuits and which is operated with operating parameters giving finite non-zero error rate as well as one or more portions formed and operated to provide a zero error rate.

摘要翻译： 集成电路包括具有错误检测和误差校正电路的一个或多个部分，并且其操作参数给出有限的非零误码率以及形成和操作以提供零错误率的一个或多个部分。

公开(公告)号：US08407537B2

公开(公告)日：2013-03-26

申请号：US12923908

申请日：2010-10-13

申请人： Krisztian Flautner ,  Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge

发明人： Krisztian Flautner ,  Todd Michael Austin ,  David Theodore Blaauw ,  Trevor Nigel Mudge

IPC分类号： G06F1/08 ,  G06F11/30

CPC分类号： G06F11/1695 ,  G06F11/0721 ,  G06F11/0793 ,  G06F11/104 ,  G06F11/1608 ,  G06F11/167 ,  G06F11/183

摘要： An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.

摘要翻译： 集成电路包括多个处理级，每个处理级包括处理逻辑1014，非延迟信号捕获元件1016，延迟信号捕获元件1018和比较器1024.非延迟信号捕获元件1016捕获来自 处理逻辑1014处于非延迟捕获时间。 在稍后延迟的捕获时间，延迟信号捕获元件1018还从处理逻辑1014捕获一个值。错误检测电路1026和纠错电路1028检测并校正延迟值中的随机误差并提供错误检查的延迟 比较器1024比较错误检查的延迟值和非延迟值，并且如果它们不相等，则这表示非延迟值被太早捕获，并且应该被错误检查的延迟值替换 值。 非延迟值在其捕获之后立即传递到后续处理阶段，因此使用错误恢复机制来抑制后续处理阶段发生的错误处理，例如选通时钟并允许正确的信号值传播 在重新启动时钟之前通过后续的处理逻辑。 调整集成电路的工作参数，例如时钟频率，工作电压，主体偏置电压，温度等，以便以提高整体性能的方式保持有限的非零错误率。

公开(公告)号：US08335122B2

公开(公告)日：2012-12-18

申请号：US12292148

申请日：2008-11-12

申请人： Ronald George Dreslinski, Jr. ,  Gregory Kengho Chen ,  Trevor Nigel Mudge ,  David Theodore Blaauw ,  Dennis Sylvester

发明人： Ronald George Dreslinski, Jr. ,  Gregory Kengho Chen ,  Trevor Nigel Mudge ,  David Theodore Blaauw ,  Dennis Sylvester

IPC分类号： G11C5/14

CPC分类号： G06F12/0897 ,  G06F12/0864 ,  G06F2212/1028 ,  Y02D10/13

摘要： A data processing apparatus is provided having a cache memory comprising a data storage array and a tag array and a cache controller coupled to the cache memory responsive to a cache access request from processing circuitry to perform cache look ups. The cache memory is arranged such that it has a first memory cell group configured to operate in a first voltage domain and a second memory cell group configured to operate in a second voltage domain that is different from the first voltage domain. A corresponding data processing method is also provided.

摘要翻译： 提供一种数据处理装置，其具有包括数据存储阵列和标签阵列的高速缓存存储器，以及响应于来自处理电路执行高速缓存查找的高速缓存访​​问请求而耦合到高速缓冲存储器的高速缓存控制器。 高速缓冲存储器被布置成使得其具有被配置为在第一电压域中操作的第一存储单元组和被配置为在不同于第一电压域的第二电压域中操作的第二存储单元组。 还提供了相应的数据处理方法。

公开(公告)号：US08185812B2

公开(公告)日：2012-05-22

申请号：US11636716

申请日：2006-12-11

申请人： Shidhartha Das ,  David Theodore Blaauw ,  David Michael Bull

发明人： Shidhartha Das ,  David Theodore Blaauw ,  David Michael Bull

IPC分类号： G06F11/00

CPC分类号： G06F11/1695 ,  G06F11/0721 ,  G06F11/0793 ,  G06F11/104 ,  G06F11/1608 ,  G06F11/167 ,  G06F11/183

摘要： An integrated circuit 2 includes logic circuitry 10 and sequential storage elements 8. Both the logic circuit 10 and sequential storage elements 8 can be subject to particle strikes giving rise to single event upset errors. These single event upset errors can be detected by detecting a transition in the stored value stored by the sequential storage elements 8 occurring outside of a valid transition period associated with that sequential storage element 8.

摘要翻译： 集成电路2包括逻辑电路10和顺序存储元件8.逻辑电路10和顺序存储元件8都可能经受粒子撞击，从而引起单事件失真错误。 可以通过检测在与该顺序存储元件8相关联的有效过渡时段之外发生的顺序存储元件8存储的存储值中的转变来检测这些单事件中断错误。

公开(公告)号：US08107290B2

公开(公告)日：2012-01-31

申请号：US12078547

申请日：2008-04-01

申请人： Yoonmyung Lee ,  Michael John Wieckowski ,  David Theodore Blaauw ,  Dennis Michael Chen Sylvester

发明人： Yoonmyung Lee ,  Michael John Wieckowski ,  David Theodore Blaauw ,  Dennis Michael Chen Sylvester

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0416 ,  G11C16/0441 ,  G11C2216/10 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11558 ,  H01L28/40

摘要： A memory cell structure for a memory device includes a read transistor having a floating gate node, a tunnelling capacitor, and a coupling capacitor stack. The tunnelling capacitor is connected to the floating gate node and has a first programming terminal, and the coupling capacitor stack is connected to the floating gate node and has a second programming terminal. The coupling capacitor stack includes at least two coupling capacitors arranged in series between the floating gate node and the second programming terminal, with the coupling capacitor stack having a larger capacitance than the tunnelling capacitor. Such a memory cell structure is efficient in terms of area, and can be manufactured using standard CMOS logic manufacturing processes, thereby avoiding some of the complexities involved in the production of conventional EEPROM and Flash memory devices.

摘要翻译： 用于存储器件的存储单元结构包括具有浮置栅极节点的读取晶体管，隧穿电容器和耦合电容器堆叠。 隧道电容器连接到浮动栅极节点并具有第一编程端子，耦合电容器堆叠连接到浮动栅极节点并具有第二编程端子。 耦合电容器堆叠包括串联布置在浮动栅极节点和第二编程端子之间的至少两个耦合电容器，耦合电容器堆叠具有比隧道电容器更大的电容。 这样的存储单元结构在面积上是有效的，并且可以使用标准CMOS逻辑制造工艺来制造，从而避免了常规EEPROM和闪存器件的生产中涉及的一些复杂性。