公开(公告)号：US5546597A

公开(公告)日：1996-08-13

申请号：US203050

申请日：1994-02-28

申请人： Robert W. Martell ,  Glenn J. Hinton ,  Michael A. Fetterman ,  David B. Papworth ,  Robert P. Colwell ,  Andrew F. Glew

发明人： Robert W. Martell ,  Glenn J. Hinton ,  Michael A. Fetterman ,  David B. Papworth ,  Robert P. Colwell ,  Andrew F. Glew

IPC分类号： G06F9/38 ,  G06F9/345

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885

摘要： An instruction dispatch circuit is disclosed that improves instruction execution throughput for a processor. The instruction dispatch circuit comprises an instruction buffer with a plurality of instruction entries and a content addressable memory array having at least one cam entry corresponding to each instruction entry. Each cam entry stores at least one source tag for the corresponding instruction entry. The content addressable memory array matches to a result tag from an execution circuit over a result bus, wherein the execution circuit transfers the result tag over the result bus at least one clock cycle before transferring a corresponding result data value over the result bus. Each cam entry generates a cam match signal used to determine whether data dependent instruction are ready for dispatch.

摘要翻译： 公开了一种提高处理器的指令执行吞吐量的指令调度电路。 指令调度电路包括具有多个指令条目的指令缓冲器和具有对应于每个指令条目的至少一个凸轮条目的内容可寻址存储器阵列。 每个凸轮条目存储用于相应指令条目的至少一个源标签。 内容可寻址存储器阵列通过结果总线与来自执行电路的结果标签相匹配，其中执行电路在通过结果总线传送相应的结果数据值之前至少一个时钟周期在结果总线上传送结果标签。 每个凸轮条目产生一个凸轮匹配信号，用于确定数据相关指令是否准备好进行发送。

公开(公告)号：US5452426A

公开(公告)日：1995-09-19

申请号：US177240

申请日：1994-01-04

申请人： David B. Papworth ,  Glenn J. Hinton ,  Michael A. Fetterman ,  Robert P. Colwell ,  Andrew F. Glew

发明人： David B. Papworth ,  Glenn J. Hinton ,  Michael A. Fetterman ,  Robert P. Colwell ,  Andrew F. Glew

IPC分类号： G06F9/38 ,  G06F9/24 ,  G06F9/28

CPC分类号： G06F9/30167 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857

摘要： A mechanism for coordinating source data in a processor, wherein a decode circuit issues instructions comprising at least one immediate valid flag and at least one logical register source. The immediate valid flag indicates whether an immediate operand for the instruction is available on an immediate data bus, and the logical register source specifies a physical register or a committed state register. A speculative result data value and a speculative source valid flag are read from the physical register, and a committed result data value is read from the committed state register. The speculative result data value and the speculative source valid flag or the committed result data value and the committed source valid flag provide a source data value and a source data valid flag for scheduling an execution of the instruction.

摘要翻译： 一种用于在处理器中协调源数据的机制，其中解码电路发出包括至少一个即时有效标志和至少一个逻辑寄存器源的指令。 即时有效标志指示在立即数据总线上是否有指令的立即操作数可用，逻辑寄存器源指定物理寄存器或提交状态寄存器。 从物理寄存器读取推测结果数据值和推测源有效标志，并从承诺状态寄存器读取提交结果数据值。 推测结果数据值和推测源有效标志或提交结果数据值和提交的源有效标志提供源数据值和源数据有效标志，用于调度指令的执行。

公开(公告)号：US5471633A

公开(公告)日：1995-11-28

申请号：US205842

申请日：1994-03-01

申请人： Robert P. Colwell ,  Andrew F. Glew ,  David B. Papworth ,  Glenn J. Hinton ,  David W. Clift

发明人： Robert P. Colwell ,  Andrew F. Glew ,  David B. Papworth ,  Glenn J. Hinton ,  David W. Clift

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F7/00

CPC分类号： G06F9/3824 ,  G06F9/30112 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A register alias table unit (RAT) with an idiom recognition mechanism for overriding partial width conditions stalls is described. A partial width stall condition occurs during the RAT renaming process when a logical source register being renamed is larger than the corresponding physical source register pointed to by a renaming table. An idiom recognizer detects uops that zero their logical destination register and sets and clears zero bits in an iRAT array accordingly. The zero bits indicate which portions of an entry's physical source register are known to be zeros. A partial width stall override mechanism overrides a partial width stall condition when the zero bits for the physical source register causing the partial width stall indicate that the "missing" portion of the physical source register contains zeros. The performance of a microprocessor implementing such a RAT renaming mechanism with an idiom recognizer is improved because common partial width stalls are avoided.

摘要翻译： 描述了具有用于覆盖部分宽度条件失速的习惯识别机制的寄存器别名表单元（RAT）。 当重新命名的逻辑源寄存器大于重命名表指向的相应物理源寄存器时，在RAT重命名过程期间发生部分宽度失速状况。 成语识别器检测uops，使其逻辑目标寄存器为零，并相应地设置和清除iRAT阵列中的零位。 零位指示条目的物理源寄存器的哪些部分已知为零。 当导致部分宽度失速的物理源寄存器的零位指示物理源寄存器的“丢失”部分包含零时，部分宽度失速覆盖机制将覆盖部分宽度失速条件。 通过习惯识别器实现这种RAT重命名机构的微处理器的性能得到改善，因为避免了普通的部分宽度档位。

公开(公告)号：US5778407A

公开(公告)日：1998-07-07

申请号：US667241

申请日：1996-06-21

申请人： Andrew F. Glew ,  Glenn J. Hinton ,  David B. Papworth ,  Michael Alan Fetterman ,  Robert P. Colwell ,  Frederick Jay Pollack

发明人： Andrew F. Glew ,  Glenn J. Hinton ,  David B. Papworth ,  Michael Alan Fetterman ,  Robert P. Colwell ,  Frederick Jay Pollack

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/06

CPC分类号： G06F12/0888 ,  G06F12/1027 ,  G06F2212/206

摘要： A circuit comprising a number of range registers and complimentary decoding/matching circuits is provided to a processor for determining the memory type of a physical address, thereby allowing memory operating characteristics to be determined as soon as the physical address is available in an execution stage preceding cache access. Additionally, a memory type field is provided to each address translation lookaside buffer entry of the data and instruction memory subsystem for storing the determined memory type, and the memory type determination circuit is disposed in the page miss handler, thereby allowing memory type to be determined at the same time when the physical address is determined.

摘要翻译： 包括多个范围寄存器和互补解码/匹配电路的电路被提供给处理器，用于确定物理地址的存储器类型，由此一旦物理地址在前面的执行阶段可用就允许确定存储器操作特性 缓存访问。 此外，存储器类型字段被提供给用于存储确定的存储器类型的数据和指令存储器子系统的每个地址转换后备缓冲器条目，并且存储器类型确定电路被布置在页面未命中处理器中，从而允许确定存储器类型 同时确定物理地址。

公开(公告)号：US06047369A

公开(公告)日：2000-04-04

申请号：US204521

申请日：1994-02-28

申请人： Robert P. Colwell ,  Andrew F. Glew ,  Atiq A. Bajwa ,  Glenn J. Hinton ,  Michael A. Fetterman

发明人： Robert P. Colwell ,  Andrew F. Glew ,  Atiq A. Bajwa ,  Glenn J. Hinton ,  Michael A. Fetterman

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/30032 ,  G06F9/30094 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885

摘要： A mechanism and method for renaming flags within a register alias table ("RAT") to increase processor parallelism and also providing and using flag masks associated with individual instructions. In order to reduce the amount of data dependencies between instructions that are concurrently processed, the flags used by these instructions are renamed. In general, a RAT unit provides register renaming to provide a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set (such as the Intel architecture or PowerPC or Alpha designs, for instance) to eliminate false data dependencies between instructions that reduce overall superscalar processing performance for the microprocessor. The renamed flag registers contain several flag bits and various flag bits may be updated or read by different instructions. Also, static and dynamic flag masks are associated with particular instructions and indicate which flags are capable of being updated by a particular instruction and also indicate which flags are actually updated by the instruction. Static flag masks are used in flag renaming and dynamic flag masks are used at retirement. The invention also discovers cases in which a flag register is required that is a superset of the previously renamed flag register portion.

摘要翻译： 一种用于重命名寄存器别名表（“RAT”）中的标志以增加处理器并行性并且还提供和使用与各个指令相关联的标志掩码的机制和方法。 为了减少并发处理的指令之间的数据依赖性，这些指令使用的标志被重命名。 通常，RAT单元提供寄存器重命名以提供比通常在给定宏架构的逻辑寄存器集（例如Intel架构或PowerPC或Alpha设计）内通常可用的更大的物理寄存器集，以消除指令之间的虚假数据依赖性 这降低了微处理器的整体超标量处理性能。 重命名的标志寄存器包含几个标志位，各种标志位可能被不同的指令更新或读取。 此外，静态和动态标志掩码与特定指令相关联，并且指示哪些标志能够被特定指令更新，并且还指示哪些标志实际上被指令更新。 在标志重命名中使用静态标志掩码，退休时使用动态标志掩码。 本发明还发现需要作为先前重命名的标志寄存器部分的超集的标志寄存器的情况。

公开(公告)号：US6101597A

公开(公告)日：2000-08-08

申请号：US176370

申请日：1993-12-30

申请人： Robert P. Colwell ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

发明人： Robert P. Colwell ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3824 ,  G06F9/383

摘要： Maximum throughput or "back-to-back" scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the prospective determination of the availability of a source operand before the operand itself is actually computed as a result of the execution of another instruction. Storage addresses of the source operands of an instruction are stored in a content addressable memory (CAM). Before an instruction is executed and its result data written back, the storage location address of the result is provided to the CAM and associatively compared with the source operand addresses stored therein. A CAM match and its accompanying match bit indicate that the result of the instruction to be executed will provide a source operand to the dependent instruction waiting in the reservation station. Using a bypass mechanism, if the operand is computed after dispatch of the dependent instruction, then the source operand is provided directly from the execution unit computing the source operand to a source operand input of the execution unit executing the dependent instruction.

摘要翻译： 通过最大化处理器确定依赖指令的源操作数的可用性的效率，并将这些操作数提供给执行依赖的执行单元，从而实现流水线处理器中相关指令的最大吞吐量或“背对背” 指令。 这两个操作通过多个机制来实现。 用于确定源操作数的可用性以及因此用于发送到可用执行单元的依赖指令的准备的机制依赖于在操作数本身实际计算之前源操作数的可用性的预期确定 执行另一条指令。 指令的源操作数的存储地址存储在内容可寻址存储器（CAM）中。 在执行指令并且其结果数据被写回之前，将结果的存储位置地址提供给CAM并与存储在其中的源操作数地址相关联地进行比较。 CAM匹配及其伴随的匹配位指示要执行的指令的结果将为在保留站等待的从属指令提供源操作数。 使用旁路机制，如果在分派依赖指令之后计算操作数，则将操作数从执行单元直接提供到计算源操作数到执行依赖指令的执行单元的源操作数输入。

公开(公告)号：US5497493A

公开(公告)日：1996-03-05

申请号：US174850

申请日：1993-12-29

申请人： Robert P. Colwell ,  Andrew F. Glew

发明人： Robert P. Colwell ,  Andrew F. Glew

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3824 ,  G06F9/30112 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A high byte right-shift detection mechanism with a register alias table unit (RAT) for selectively causing right-shifting of high byte physical source register data before operations are executed within a microprocessor is described. A high byte right-shift condition occurs when a logical source register that is presented to the RAT for renaming is a high byte register and the corresponding physical source register selected by the RAT is not right-adjusted. A non right-adjusted physical source register is detected when either the physical source register is an architectural state register or the physical source register is a larger width register that includes the renamed high byte register. The high byte right-shift detection mechanism detects a high byte shirt-right condition when a logical source register is renamed and generates shift bits and zero extend bits to control the right-shifting and zero extending of the data in the correspondingly renamed physical source register before execution by an execution unit that assumes right-adjusted input data. Right-adjusted result data from the execution unit is stored in a physical destination register (a speculative state register) in the re-order buffer (ROB) until retirement. If the RAT renames another high byte logical source register to source that physical destination register before the register retires, right-shifting of the physical destination register data is not required because the data is already right-adjusted. At retirement, physical destination register data corresponding to a high byte logical destination register is left-shifted and stored in the high byte register of a non-speculative state register in the retirement register file (RRF).

摘要翻译： 描述了具有用于在微处理器内执行操作之前选择性地引起高字节物理源寄存器数据的右移的寄存器别名表单元（RAT）的高字节右移检测机制。 当呈现给RAT以进行重命名的逻辑源寄存器是高字节寄存器并且由RAT选择的对应物理源寄存器未被正确调整时，发生高字节右移条件。 当物理源寄存器是架构状态寄存器或物理源寄存器是包括重命名的高字节寄存器的较大宽度寄存器时，检测到非右调整物理源寄存器。 当逻辑源寄存器被重命名时，高字节右移检测机构检测到高字节衬衫右条件，并产生移位位和零扩展位以控制相应重命名的物理源寄存器中的数据的右移和零扩展 在由执行单元执行之前，该执行单元承担右调整的输入数据。 来自执行单元的右调整结果数据被存储在重新排序缓冲器（ROB）中的物理目的地寄存器（推测状态寄存器）中，直到退出。 如果在注册器退出之前，RAT重新命名另一个高字节逻辑源寄存器来源物理目标寄存器，则不需要对物理目标寄存器数据进行右移，因为数据已经被正确调整。 在退休时，对应于高字节逻辑目标寄存器的物理目标寄存器数据被左移并存储在退出寄存器堆（RRF）中的非推测状态寄存器的高字节寄存器中。

公开(公告)号：US5524262A

公开(公告)日：1996-06-04

申请号：US443189

申请日：1995-05-17

申请人： Robert P. Colwell ,  Andrew F. Glew

发明人： Robert P. Colwell ,  Andrew F. Glew

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3828 ,  G06F9/30112 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A bypass mechanism within a register alias table unit (RAT) for handling source-destination dependencies between operands of a given set of operations issued simultaneously within a superscalar microproessor. Operations of the given set are presented in program order and data dependencies occur when a source register of particular operation is also utilizes as a destination register of a preceding operation within the given set of operations. At this occurence, the initial read of the RAT unit will not have supplied the most current rename of the source register. The present invention includes a comparison mechanism to detect this condition. Also included is a bypass mechanism for bypassing the physical source register output by the initial read of the RAT unit with a recently allocated physical destination register assigned to the preceding operation having the matched physical destination register. In general the RAT unit provides register renaming to provide a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set (such as the Intel architecture or PowerPC or Alpha designs, for instance) to eliminate false data dependencies that reduce overall superscalar processing performance for the microprocessor. The bypass mechanism of the present invention handles both floating point and integer registers and, in addition, a second bypass mechanism is included in the RAT priority write operation.

摘要翻译： 寄存器别名表单元（RAT）内的旁路机制，用于处理在超标量微处理器内同时发出的给定操作集的操作数之间的源 - 目的地依赖关系。 给定集合的操作以程序顺序呈现，并且当特定操作的源寄存器也用作给定操作集合中的先前操作的目标寄存器时，发生数据依赖性。 在这种情况下，RAT单元的初始读取将不会提供源寄存器的最新的重命名。 本发明包括用于检测该状况的比较机构。 还包括旁路机构，用于通过用分配给具有匹配的物理目的地寄存器的先前操作的最近分配的物理目的地寄存器来初始读取RAT单元旁路物理源寄存器输出。 通常，RAT单元提供寄存器重命名以提供比通常在给定宏架构的逻辑寄存器集（例如Intel架构或PowerPC或Alpha设计）内通常可用的更大的物理寄存器集，以消除虚假数据依赖性，从而减少整体 微处理器的超标量处理性能。 本发明的旁路机构处理浮点和整数寄存器，并且另外在RAT优先级写入操作中包括第二旁路机制。

公开(公告)号：US5446912A

公开(公告)日：1995-08-29

申请号：US174841

申请日：1993-12-29

申请人： Robert P. Colwell ,  Andrew F. Glew

发明人： Robert P. Colwell ,  Andrew F. Glew

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F15/78

CPC分类号： G06F9/3824 ,  G06F9/30112 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A partial width stall mechanism within a register alias table unit (RAT) for handling partial width data dependencies of a given set of operations issued simultaneously within a superscalar microprocessor. Operations of the given set are presented to the RAT in program order and partial width data dependencies occur when the size of a logical source register that is presented to the RAT for renaming to a corresponding physical source register is larger than the corresponding physical source register selected by the RAT. At this occurrence, the data required by the logical source register to be renamed does not reside in any one physical source register. Therefore, renaming of that logical register must be stalled until the data for that logical register is accumulated into one location. The data will be so accumulated when the last operation to have written the physical source register is retired and is, therefore, nonspeculative. The present invention includes a size comparison mechanism to detect the partial width stall condition. Also included is a partial width stall mechanism for preventing the renaming process from operating when the partial width stall condition is detected. In general the RAT unit provides register renaming to provide a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set to eliminate false data dependencies that would otherwise reduce overall superscalar processing performance for the microprocessor.

摘要翻译： 寄存器别名表单元（RAT）内的部分宽度失速机制，用于处理在超标量微处理器内同时发出的给定操作集合的部分宽度数据依赖性。 给定集合的操作以程序顺序呈现给RAT，并且当向RAT提供重新命名到对应的物理源寄存器的逻辑源寄存器的大小大于选择的相应物理源寄存器时，发生部分宽度数据依赖性 由RAT。 在这种情况下，要重命名的逻辑源寄存器所需的数据不在任何一个物理源寄存器中。 因此，必须停止该逻辑寄存器的重命名，直到该逻辑寄存器的数据被累积到一个位置。 当写入物理源寄存器的最后一个操作被退出时，数据将被如此累积，因此是非限制性的。 本发明包括检测局部宽度失速状态的尺寸比较机构。 还包括部分宽度失速机构，用于当检测到部分宽度失速条件时防止重命名过程的操作。 通常，RAT单元提供寄存器重命名以提供比给定宏架构的逻辑寄存器集中通常可用的更大的物理寄存器集合，以消除否则会降低微处理器的整体超标量处理性能的假数据依赖性。

公开(公告)号：US5727176A

公开(公告)日：1998-03-10

申请号：US611950

申请日：1996-03-06

申请人： David W. Clift ,  James M. Arnold ,  Robert P. Colwell ,  Andrew F. Glew

发明人： David W. Clift ,  James M. Arnold ,  Robert P. Colwell ,  Andrew F. Glew

IPC分类号： G06F9/315 ,  G06F9/38 ,  G06F12/02

CPC分类号： G06F9/30032 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  Y10S707/99936

摘要： A data processor includes a plurality of physical registers and a decoder that decodes a stream of instructions into micro-operations which include speculative operations specifying associated logical registers. The data processor further includes a register-alias table having a plurality of addressable entries corresponding to logical registers, specified by the speculative operations. Each entry of the register-alias table contains a register pointer to a corresponding physical register. The processor further includes a retirement register file that maintains register values of non-speculative operations, and a retirement array that maintains a retirement ordering for the retirement register file. Both the register-alias table and retirement array are updated by circuitry that is responsive to a register exchange operation; the circuitry swapping register pointers associated with first and second entries, respectively.

摘要翻译： 数据处理器包括多个物理寄存器和将指令流解码为微操作的解码器，其包括指定关联的逻辑寄存器的推测性操作。 数据处理器还包括一个寄存器别名表，其具有与由推测操作指定的逻辑寄存器对应的多个可寻址条目。 寄存器别名表的每个条目包含一个到相应物理寄存器的寄存器指针。 处理器还包括维护非投机操作的注册值的退休登记文件，以及维持退休登记文件的退休顺序的退休数组。 寄存器别名表和退出数组都由响应于寄存器交换操作的电路来更新; 电路交换与第一和第二条目相关联的寄存器指针。