公开(公告)号：US20120244825A1

公开(公告)日：2012-09-27

申请号：US13070683

申请日：2011-03-24

申请人： Brian D. Green ,  Jing Li ,  Thomas Glen Ragan ,  Michael R. May

发明人： Brian D. Green ,  Jing Li ,  Thomas Glen Ragan ,  Michael R. May

IPC分类号： H04B17/00

CPC分类号： H03G3/3073 ,  H03G3/3052 ,  H04B17/318

摘要： A radio frequency (RF) signal is received in a receiver, and various counts based on information from the signal can be obtained. Counts of a number of samples of the RF signal exceeding first and second thresholds can be accumulated during an accumulation window. From the first of these counts, it can be determined if the count exceeds a first metric corresponding to a first predetermined count value, and if so, a gain of an RF gain element can be reduced. From the second of these counts it can be determined if this count exceeds a second metric corresponding to a second predetermined count value, and if not, the gain can be increased.

摘要翻译： 在接收机中接收射频（RF）信号，并且可以获得基于来自信号的信息的各种计数。 可以在累积窗口期间累积超过第一和第二阈值的RF信号的多个样本的计数。 从这些计数中的第一个可以确定计数是否超过对应于第一预定计数值的第一度量，如果是，则可以减小RF增益元件的增益。 从这些计数中的第二个可以确定该计数是否超过对应于第二预定计数值的第二度量，如果不是，则可以增加增益。

公开(公告)号：US07940132B2

公开(公告)日：2011-05-10

申请号：US11862312

申请日：2007-09-27

申请人： Michael R. May ,  Raymond L. Vargas

发明人： Michael R. May ,  Raymond L. Vargas

IPC分类号： H03K21/10

CPC分类号： H03L7/0995 ,  G06F1/06

摘要： A clock system includes a phase locked loop, a phase divider, and a control module. The phase locked loop (PLL) produces a plurality of phase-offset output oscillations. The phase divider generates a clock signal from one or more of the plurality of phase-offset output oscillations based on a phase divider control signal. The control module generates the phase divider control signal based on a desired setting for the clock signal.

摘要翻译： 时钟系统包括锁相环，相位分配器和控制模块。 锁相环（PLL）产生多个相位偏移输出振荡。 相位分离器基于相位分配器控制信号从多个相位偏移输出振荡中的一个或多个产生时钟信号。 控制模块基于时钟信号的期望设置产生相位分配器控制信号。

公开(公告)号：US07809345B2

公开(公告)日：2010-10-05

申请号：US11796057

申请日：2007-04-26

申请人： Michael R. May

发明人： Michael R. May

IPC分类号： H04B1/06

CPC分类号： H03L7/081 ,  H03L7/089 ,  H03L7/0996 ,  H03L7/1974 ,  H03L2207/50

摘要： A digital phase locked loop (PLL) includes a digital phase detector, a digital loop filter, a digitally controlled oscillation module, and a variable feedback divider. The digital phase detector is coupled to produce a difference signal based on a phase difference between a reference oscillation and a feedback oscillation. The digital loop filter is coupled to process the difference signal to produce a control signal. The digitally controlled oscillation module is coupled to generate an output oscillation based on the control signal. The variable feedback divider is coupled to produce the feedback oscillation from the output oscillation based on a divider value and a controlled variable delay.

摘要翻译： 数字锁相环（PLL）包括数字相位检测器，数字环路滤波器，数字控制振荡模块和可变反馈分频器。 数字相位检测器被耦合以基于参考振荡和反馈振荡之间的相位差产生差分信号。 数字环路滤波器被耦合以处理差分信号以产生控制信号。 数字控制振荡模块被耦合以基于控制信号产生输出振荡。 可变反馈分压器被耦合以基于分频器值和受控变量延迟从输出振荡产生反馈振荡。

公开(公告)号：US20100156390A1

公开(公告)日：2010-06-24

申请号：US12721014

申请日：2010-03-10

申请人： Matthew D. Felder ,  Michael R. May

发明人： Matthew D. Felder ,  Michael R. May

IPC分类号： H03H7/00

CPC分类号： H04L27/14 ,  H03F3/189 ,  H03F3/343 ,  H03G3/3068

摘要： A method for signal strength detection begins by comparing a signal strength representation of a signal with a signal strength representation of a reference signal. The method continues by adjusting, when the signal strength representation of the signal compares unfavorably with the signal strength representation of the reference signal, at least one of the signal strength representation of the signal and the signal strength representation of the reference signal until the signal strength representation of the signal compares favorably with the signal strength representation of the reference signal. The method continues by determining signal strength of the signal based on the adjusting of the signal strength representation of the signal and signal strength of the reference signal.

摘要翻译： 用于信号强度检测的方法开始于将信号的信号强度表示与参考信号的信号强度表示进行比较。 该方法通过调节信号的信号强度表示与参考信号的信号强度表示不利地相比较，信号的信号强度表示和参考信号的信号强度表示中的至少一个直到信号强度 信号的表示与参考信号的信号强度表示相当。 该方法通过基于信号的信号强度表示和参考信号的信号强度的调整来确定信号的信号强度来继续。

公开(公告)号：US07656968B2

公开(公告)日：2010-02-02

申请号：US11287571

申请日：2005-11-22

申请人： Erich Lowe ,  Michael R. May

发明人： Erich Lowe ,  Michael R. May

IPC分类号： H03K9/00 ,  H04L27/00

CPC分类号： H04B15/02 ,  H04B2215/065

摘要： A system on a chip integrated circuit includes an analog front end for receiving a received radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies, and for converting a selected one of the plurality of channel signals into a digital signal. A digital clock generator generates a digital clock signal at a digital clock frequency that varies based on the selected one of the plurality of channel signals. The digital clock frequency, and integer multiples of the digital clock frequency, are not substantially equal to the carrier frequency of the selected one of the plurality of channel signals. A digital section converts the digital signal into at least one audio signal that corresponds to the selected one of the plurality of channels, based on the digital clock signal.

摘要翻译： 片上集成电路系统包括：模拟前端，用于接收具有多个信道信号的接收无线电信号，多个信道信号中的每一个以对应的多个载波频率中的一个调制，并且用于将所选择的一个 的多个信道信号转换为数字信号。 数字时钟发生器以数字时钟频率产生数字时钟信号，该数字时钟频率根据所选择的多个信道信号之一而变化。 数字时钟频率和数字时钟频率的整数倍基本上不等于多个信道信号中所选择的一个的载波频率。 数字部分基于数字时钟信号将数字信号转换成对应于多个信道中所选择的一个信道的至少一个音频信号。

公开(公告)号：US07535287B2

公开(公告)日：2009-05-19

申请号：US11446612

申请日：2006-06-05

申请人： Michael R. May ,  Marcus William May

发明人： Michael R. May ,  Marcus William May

IPC分类号： G05F1/10 ,  G06F1/00

CPC分类号： H02M1/084

摘要： A system includes a first semiconductor device, a second semiconductor device, and an external crystal oscillator. The first semiconductor device includes a source voltage output and an external pin input. The first semiconductor device includes a direct current-to-direct current (DC-DC) converter circuit that provides the source voltage output. The second semiconductor device includes a source voltage input that is coupled to the source voltage output of the first semiconductor device and includes a clock signal output. The external crystal oscillator is coupled via an input of the second semiconductor device to a first oscillator clock generation circuit.

摘要翻译： 一种系统包括第一半导体器件，第二半导体器件和外部晶体振荡器。 第一半导体器件包括源极电压输出和外部引脚输入。 第一半导体器件包括提供源极电压输出的直流 - 直流（DC-DC）转换器电路。 第二半导体器件包括耦合到第一半导体器件的源极电压输出并包括时钟信号输出的源极电压输入。 外部晶体振荡器经由第二半导体器件的输入耦合到第一振荡器时钟产生电路。

公开(公告)号：US07391347B2

公开(公告)日：2008-06-24

申请号：US11287572

申请日：2005-11-22

申请人： Michael R. May ,  Erich Lowe

发明人： Michael R. May ,  Erich Lowe

IPC分类号： H03M1/48

CPC分类号： H04B15/02 ,  H04B2215/065 ,  H04H40/18

摘要： A system on a chip integrated circuit includes a first digital module a second digital module such that the first digital module and the second digital module are operably coupled to generate an output signal based on an input signal, based on the first digital clock signal and the second digital clock signal. A digital clock generator generates a base clock signal at a base clock frequency that varies based on a control signal and generates a first digital clock signal having a substantially constant number of first digital clock cycles over a predetermined period and for generating a second digital clock signal having a substantially constant number of second digital clock cycles over the predetermined period.

摘要翻译： 片上集成电路系统包括第一数字模块第二数字模块，使得第一数字模块和第二数字模块可操作地耦合以基于输入信号基于第一数字时钟信号和 第二数字时钟信号。 数字时钟发生器以基于时钟频率的基本时钟信号产生基于控制信号而变化的基本时钟信号，并且产生在预定时段内具有基本上恒定数量的第一数字时钟周期的第一数字时钟信号，并产生第二数字时钟信号 在预定时段内具有基本恒定数量的第二数字时钟周期。

公开(公告)号：US07106715B1

公开(公告)日：2006-09-12

申请号：US09990896

申请日：2001-11-16

申请人： James Robert Kelton ,  Michael David Cave ,  James Ward Girardeau, Jr. ,  Michael R. May ,  Paul Morris Astrachan ,  Anselmo Pilla ,  James Doyle ,  Shawn Saleem ,  Mathew A. Rybicki

发明人： James Robert Kelton ,  Michael David Cave ,  James Ward Girardeau, Jr. ,  Michael R. May ,  Paul Morris Astrachan ,  Anselmo Pilla ,  James Doyle ,  Shawn Saleem ,  Mathew A. Rybicki

IPC分类号： H04Q7/24 ,  H04Q7/20 ,  H04L12/26

CPC分类号： H04L41/0803 ,  H04L41/0896 ,  H04W28/18 ,  H04W52/241 ,  H04W52/28

摘要： A system is provided for transmitting data to a plurality of devices. A data source receives data from a video broadcasting source, such as a digital television provides, through a data cable. The data source identifies devices to receive particular sets of data, such as particular programs, from the data cable. The data source identifies particular settings for transmitting to particular devices. The data source adjusts a transmission power to a first device to efficiently provide data reliably to the first device. The data source can assign more or less power for transmitting data to the first device. The data source provides data to the source device using a first data channel. The data source provides data to a second device using a second data channel. The data source receives acknowledgements and control information from the first device and the second device using the second data channel.

摘要翻译： 提供了一种用于将数据发送到多个设备的系统。 数据源通过数据电缆从诸如数字电视的视频广播源接收数据。 数据源识别从数据电缆接收特定数据集合（例如特定程序）的设备。 数据源标识用于发送到特定设备的特定设置。 数据源调整到第一设备的传输功率，以有效地向第一设备提供数据。 数据源可以分配更多或更少的功率以将数据发送到第一设备。 数据源使用第一数据通道向源设备提供数据。 数据源使用第二数据信道向第二设备提供数据。 数据源使用第二数据信道从第一设备和第二设备接收确认和控制信息。

公开(公告)号：US06522275B2

公开(公告)日：2003-02-18

申请号：US09779158

申请日：2001-02-08

申请人： Michael R. May

发明人： Michael R. May

IPC分类号： H03M300

CPC分类号： H03H17/0621 ,  H03M3/418 ,  H03M3/462

摘要： A method and apparatus for sample rate conversion in an analog to digital converter includes processing that begins by converting an analog input signal into a stream of digital data. The processing continues by determining an up sampling value and a down sampling value based on a sample rate conversion value. The processing continues by computing a moving sum of data of the stream of data based on the up sampling value, the clock rate of the stream of data, and a predetermined filter function. The processing continues by producing a digital output value from the moving sum based on the down sampling value, wherein the digital output value is at a desired output rate.

摘要翻译： 用于模数转换器中采样率转换的方法和装置包括通过将模拟输入信号转换为数字数据流开始的处理。 通过基于采样率转换值确定上采样值和下采样值来继续处理。 该处理通过基于上采样值，数据流的时钟速率和预定的滤波器函数计算数据流的数据的移动和来继续。 该处理继续通过基于下采样值从移动和产生数字输出值，其中数字输出值处于期望的输出速率。

公开(公告)号：US06278394B1

公开(公告)日：2001-08-21

申请号：US09400257

申请日：1999-09-21

申请人： Michael R. May

发明人： Michael R. May

IPC分类号： H03M166

CPC分类号： H03M3/372 ,  H03M3/50 ,  H03M7/3026 ,  H03M7/304

摘要： An analog-to-digital or digital-to-analog system contains a converter (706). The converter is supplied with a clock signal (CLK1) at a frequency fs derived from a crystal of a frequency fs/N. The frequency fs is derived from the fs/N crystal frequency by using an edge-triggered clock multiplier 705 which multiplies the crystal frequency by the factor N. The result is a low-cost clock solution that incorporates clock jitter around a localized frequency of fs/N. Sigma delta processing circuitry (702) is then used to place a null (e.g., low gain area) in the quantization noise at the same frequency where clock jitter noise is high in order to cancel the adverse cumulative effects of these two types of noise.

摘要翻译： 模拟数字或数模转换系统包含转换器（706）。 该转换器以从频率fs / N的晶体得到的频率fs提供时钟信号（CLK1）。 通过使用将晶体频率乘以因子N的边沿触发时钟乘法器705，从fs / N晶体频率导出频率fs。结果是一种低成本的时钟解决方案，其围绕fs的局部频率 / N。 然后，Sigma增量处理电路（702）用于在时钟抖动噪声较高的相同频率处在量化噪声中放置零（例如，低增益区），以消除这两种噪声的不利累积效应。