公开(公告)号：US06272520B1

公开(公告)日：2001-08-07

申请号：US09001545

申请日：1997-12-31

申请人： Harshvardhan Sharangpani ,  Rajiv Gupta ,  Judge K. Arora

发明人： Harshvardhan Sharangpani ,  Rajiv Gupta ,  Judge K. Arora

IPC分类号： G06F900

CPC分类号： G06F9/3851 ,  G06F9/3824 ,  G06F9/3838

摘要： A method for detecting thread switch conditions provides first and second scoreboard bits for each register in a register file. The first scoreboard bit associated with a register is set when a load is generated to return data to the register. The second scoreboard bit is set if the load misses in a selected processor cache. Register read instructions are monitored, and a thread switch condition is indicated when a register read instruction to the register is detected while its first and second scoreboard bits are set.

摘要翻译： 用于检测线程切换条件的方法为寄存器文件中的每个寄存器提供第一和第二记分板位。 当产生负载以将数据返回到寄存器时，与寄存器相关联的第一记分板位置1。 如果所选处理器高速缓存中的加载丢失，则第二个记分板位置1。 监视寄存器读取指令，当在其第一和第二记分板位被置位时检测到寄存器的寄存器读取指令时指示线程切换条件。

公开(公告)号：US06205466B1

公开(公告)日：2001-03-20

申请号：US09118248

申请日：1998-07-17

申请人： Alan H. Karp ,  Rajiv Gupta ,  Arindam Banerji ,  Ernest Mak ,  Sandeep Kumar ,  Guillermo Rozas ,  Chia-Chiang Chao ,  Venkatesh Krishnan ,  Alexandre Bronstein

发明人： Alan H. Karp ,  Rajiv Gupta ,  Arindam Banerji ,  Ernest Mak ,  Sandeep Kumar ,  Guillermo Rozas ,  Chia-Chiang Chao ,  Venkatesh Krishnan ,  Alexandre Bronstein

IPC分类号： G06F900

CPC分类号： G06F9/468 ,  G06F21/6218 ,  G06F21/6236 ,  G06F2221/2141 ,  G06Q10/10 ,  Y10S707/99931 ,  Y10S707/99932

摘要： A software infrastructure for providing an open digital services marketplace including a naming manager that enables a requesting task to refer to a desired resource using a name which is local to the requesting task and a router that forwards the request to an appropriate handler for the desired resource and that enables at least one additional task to be invoked in response to the request. The infrastructure includes a permission manager that compares a set of access rights of the requesting task to the desired resource to a set of permissions associated with the desired resource such that the access rights are kept separately from the reference to the desired resource. The desired resource, the requesting task, the additional task, and a set of additional components used to handle the request are each modeled as a resource defined by a corresponding set of meta-data which includes a set of attributes and a reference to a grammar for interpreting the attributes.

摘要翻译： 一种用于提供开放数字服务市场的软件基础设施，包括命名管理器，其允许请求任务使用请求任务本地的名称引用期望的资源，以及将请求转发到所需资源的适当处理程序的路由器 并且这使得能够响应于该请求调用至少一个附加任务。 基础设施包括权限管理器，其将请求任务的一组访问权限与期望的资源进行比较，以与所需资源相关联的一组权限进行比较，使得访问权限与对期望的资源的引用分开地保持。 所需资源，请求任务，附加任务和用于处理请求的一组附加组件各自被建模为由对应的一组元数据定义的资源，该元数据包括一组属性和对语法的引用 用于解释属性。

公开(公告)号：US5941983A

公开(公告)日：1999-08-24

申请号：US881244

申请日：1997-06-24

申请人： Rajiv Gupta ,  William S. Worley, Jr.

发明人： Rajiv Gupta ,  William S. Worley, Jr.

IPC分类号： G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3869 ,  G06F9/3885

摘要： A method for executing instructions out-of-order to improve performance of a processor includes compiling the instructions of a program into separate queues along with encoded dependencies between instructions in the different queues. The processor then issues instructions from each of these queues independently, except that it enforces the encoded dependencies among instructions from different queues. If an instruction is dependent on instructions in other queues, the processor waits to issue it until the instructions on which it depends are issued. The processor includes a stall unit, comprised of a number of instruction counters for each queue, that enforces the dependencies between instructions in different queues.

摘要翻译： 用于执行无序的指令以改善处理器的性能的方法包括将程序的指令与不同队列中的指令之间的编码的依赖关系一起编译成单独的队列。 然后处理器独立地从每个这些队列发出指令，除了它强制来自不同队列的指令之间的编码依赖性。 如果指令依赖于其他队列中的指令，则处理器等待发出，直到发出依赖于其的指令。 该处理器包括一个停顿单元，包括用于每个队列的多个指令计数器，其强制在不同队列中的指令之间的依赖性。

公开(公告)号：US5787272A

公开(公告)日：1998-07-28

申请号：US871562

申请日：1997-06-10

申请人： Rajiv Gupta ,  Michael Abraham Epstein

发明人： Rajiv Gupta ,  Michael Abraham Epstein

IPC分类号： G06F15/16 ,  G06F9/45 ,  G06F9/46 ,  G06F9/52 ,  G06F15/177 ,  G06F15/80

CPC分类号： G06F9/3834 ,  G06F8/458 ,  G06F9/30087

摘要： A barrier is used to synchronize parallel processors. The barrier is "fuzzy", i.e. it includes several instructions in each instruction stream. None of the processors performing related tasks can execute an instruction after its respective fuzzy barrier until the others have finished the instruction immediately preceding their respective fuzzy barriers. Processors therefore spend less time waiting for each other. A state machine is used to keep track of synchronization states during the synchronization process.

摘要翻译： 使用屏障来同步并行处理器。 屏障是“模糊的”，即它包括每个指令流中的几个指令。 执行相关任务的处理器中的任何一个都不能在其各自的模糊屏障之后执行指令，直到其他人已经完成在它们各自的模糊屏障之前的指令。 因此，处理器花费更少的时间等待对方。 状态机用于在同步过程中跟踪同步状态。

公开(公告)号：US5721865A

公开(公告)日：1998-02-24

申请号：US588503

申请日：1996-01-18

申请人： Yooichi Shintani ,  Yoshikazu Tanaka ,  Naohiko Irie ,  William S. Worley, Jr. ,  B. Ramakrishna Rau ,  Rajiv Gupta ,  Frederic C. Amerson

发明人： Yooichi Shintani ,  Yoshikazu Tanaka ,  Naohiko Irie ,  William S. Worley, Jr. ,  B. Ramakrishna Rau ,  Rajiv Gupta ,  Frederic C. Amerson

IPC分类号： G06F9/345 ,  G06F9/38 ,  G06F12/02 ,  G06F12/08 ,  G06F17/16 ,  G06F9/34

CPC分类号： G06F9/3455 ,  G06F9/30047 ,  G06F9/30181 ,  G06F9/383 ,  G06F9/3834

摘要： To improve the function of a circuit for prefetching data accessed by a processor, a prefetch unit incorporates therein a circuit for issuing a request to read out one group of data to be prefetched and registers for holding the group of data read in response to the read request therein. The group of data are read out from a cache memory or a main memory under the control of a cache request unit. A plurality of groups of data can be prefetched. When data designation is made, the processor requests the cache memory to read a block to which the data to be prefetched belongs. A circuit is also included in the prefetch unit, wherein when prefetched data is subsequently updated by the processor, its updated data is made invalid. Elements of a vector complex in structure, such as an indexed vector or the like can be also read out. It is also possible to cope with an interrupt generated within the processor.

摘要翻译： 为了改进用于预取由处理器访问的数据的电路的功能，预取单元在其中结合有用于发出读取需要预取的一组数据的请求的电路，并且用于保存响应于读取读取的数据组的寄存器 请求。 在高速缓存请求单元的控制下，从高速缓冲存储器或主存储器读出数据组。 可以预取多组数据。 当进行数据指定时，处理器请求高速缓冲存储器读取要预取的数据所属的块。 预取单元中还包括一个电路，其中当处理器随后更新预取的数据时，其更新的数据变为无效。 也可以读出结构中的向量复合体的元素，例如索引向量等。 也可以处理处理器内产生的中断。

公开(公告)号：US5715167A

公开(公告)日：1998-02-03

申请号：US502034

申请日：1995-07-13

申请人： Rajiv Gupta ,  Barry Joe Webb

发明人： Rajiv Gupta ,  Barry Joe Webb

IPC分类号： G05B19/401 ,  G06F19/00 ,  G06G7/64 ,  G06G7/66

CPC分类号： G05B19/401 ,  G05B2219/37205 ,  G05B2219/37569 ,  G05B2219/50122

摘要： A system of accurately positioning a manufactured part in a calibrated position, involves positioning the part on a structure. Adjusting the part on the structure such that points on the surface of the part known to be accurate and drilling notches in the part at known locations. Distances from the surface of the part to the structure in `x` and `z` directions, and a rotation angle .theta. are measured. The part is then placed in a fixture having a nest plate with pins which hold the part by the notches thereby defining an axis through the part. A `z` stop is adjusted to the measured `z` distance which stops rotation of the part about the axis between the pins. An `x` stop is set to the measured x distance which stops translation of the part along the axis between the pins. The nest plate is pivotally attached to the base plate allowing the nest plate to rotate with respect to the base plate the rotational angle .theta.. This results in calibrated positioning of the part allowing maximum access to the part. Additionally, the fixture is made of X-ray transparent material, and radio-opaque tooling balls are positioned at known locations to facilitate X-ray imaging of the part for testing.

摘要翻译： 将制造的部件精确地定位在校准位置的系统涉及将部件定位在结构上。 调整结构上的零件，使得零件表面上的点已知准确，并在已知位置的零件中钻孔。 测量从零件的表面到“x”和“z”方向上的结构的距离以及旋转角度θ。 然后将该部件放置在具有嵌套板的固定装置中，所述嵌套板具有通过凹口保持该部分的销，从而限定穿过该部分的轴。 一个'z'挡块被调节到测量的'z'距离，这个距离可以阻止零件围绕销之间的轴的转动。 一个“x”挡位被设定为测量的x距离，该距离会停止沿引脚之间的轴的平移。 嵌套板枢转地附接到基板，允许嵌套板相对于基板旋转角度θ。 这导致部件的校准定位允许最大程度地访问部件。 另外，夹具由X射线透明材料制成，不透射线的工具球位于已知位置，以方便X射线成像部件进行测试。

公开(公告)号：US5532576A

公开(公告)日：1996-07-02

申请号：US226197

申请日：1994-04-11

申请人： Edward MacRobbie ,  Daryush Shamlou ,  Rajiv Gupta ,  Raouf Halim

发明人： Edward MacRobbie ,  Daryush Shamlou ,  Rajiv Gupta ,  Raouf Halim

IPC分类号： G06F1/26 ,  G05F1/56 ,  G05F3/30 ,  H02M3/07 ,  G05F1/575

CPC分类号： H02M3/07 ,  Y10S323/901

摘要： An on-board regulated voltage up-convertor for converting a first DC voltage at a first node from an electronic system to a second DC voltage for an integrated device at a second node. The convertor comprises reference generator means for generating a predetermined reference voltage at start-up, voltage regulator means coupled to said first node for regulating said first voltage at a predetermined voltage at a third node, voltage multiplier means coupled to said third node and to said second node for multiplying said predetermined voltage to generate an output voltage substantially equal to said second voltage, feedback means coupled to said second node for feeding said output voltage back to said voltage regulator means to adjust the level of said predetermined voltage at said third node according to how said output voltage is relative to said second voltage.

摘要翻译： 一种车载调节电压上变频器，用于将第一节点处的第一直流电压从电子系统转换为第二节点处的集成装置的第二直流电压。 转换器包括用于在启动时产生预定参考电压的参考发生器装置，耦合到所述第一节点的电压调节器装置，用于在第三节点处以预定电压调节所述第一电压，耦合到所述第三节点的电压倍增器装置和所述第 第二节点，用于乘以所述预定电压以产生基本上等于所述第二电压的输出电压，耦合到所述第二节点的反馈装置，用于将所述输出电压馈送回所述电压调节器装置，以根据所述第三节点调整所述预定电压的电平， 所述输出电压如何相对于所述第二电压。

公开(公告)号：US5317734A

公开(公告)日：1994-05-31

申请号：US400178

申请日：1989-08-29

申请人： Rajiv Gupta

发明人： Rajiv Gupta

IPC分类号： G06F15/16 ,  G06F9/44 ,  G06F9/45 ,  G06F15/80 ,  G06F13/00

CPC分类号： G06F8/45 ,  G06F8/458

摘要： A method of synchronizing the parallel processors of a multiple instruction stream multiprocessor employs a limited number of register channels, which may be re-used, for enforcing cross-stream data or event dependencies by passing data or event notifications in a synchronizing fashion. Cross-stream dependencies which by virtue of identified "synchronization redundancey" do not require enforcement by register channels are passed by writing to and reading from ordinary shared memory. A compiling method schedules the instructions into parallel instruction streams by reference to a directed acyclic graph (DAG), in a manner to minimize the production of cross-stream dependencies. The scheduling is determined beginning from the highest nodes in the DAG and proceeding to nodes in order of descending node height in a manner tending and tends to assign whole sub-graphs of the DAG to different processors.

摘要翻译： 同步多指令流多处理器的并行处理器的方法采用有限数量的可以重新使用的寄存器通道，以通过以同步方式传递数据或事件通知来实施交叉流数据或事件相关性。 通过识别的“同步冗余”不需要通过寄存器通道执行的跨流依赖通过写入和从普通共享存储器读取来传递。 编译方法通过参考有向非循环图（DAG）将指令调度为并行指令流，以最小化跨流依赖性的生成。 调度从DAG中的最高节点开始确定，并按照趋向下降的节点高度的顺序进行到节点，并且倾向于将DAG的整个子图分配给不同的处理器。

公开(公告)号：US4583013A

公开(公告)日：1986-04-15

申请号：US579617

申请日：1984-02-13

申请人： Rajiv Gupta

发明人： Rajiv Gupta

IPC分类号： H03K5/19 ,  H03K19/21 ,  H03K17/687

CPC分类号： H03K5/19 ,  H03K19/215

摘要： A circuit for use on an integrated circuit chip for detecting the operative connection of a crystal used to control an on-chip crystal controlled oscillator, which generates a cyclical clock signal, by detecting the presence or absence, respectively, of the cyclical clock signal and for providing an output control signal in response thereto to an on-chip terminal pad control circuit which automatically enables an on-chip terminal pad to be utilized as a clock signal output terminal pad if the cyclical clock signal presence is detected or as a clock signal input terminal pad otherwise. Also, a method of automatically switching the function of a terminal pad on an integrated circuit chip to function as a clock signal output terminal pad or as a clock signal input terminal pad in accordance with detecting the existence or non-existence of a cyclical clock signal generated on-chip.

摘要翻译： 一种在集成电路芯片上使用的用于检测用于控制片上晶体振荡器的晶体的操作连接的电路，其产生周期性时钟信号，分别通过检测周期性时钟信号的存在或不存在，以及 用于提供与片上终端焊盘控制电路相应的输出控制信号，如果检测到周期性时钟信号存在或者作为时钟信号自动使芯片上的端子焊盘用作时钟信号输出端子焊盘 输入端子垫。 另外，根据检测到循环时钟信号的存在或不存在，自动切换集成电路芯片上的端子焊盘的功能以用作时钟信号输出端子焊盘或作为时钟信号输入端子焊盘的方法 片上生成。

公开(公告)号：US10045752B2

公开(公告)日：2018-08-14

申请号：US14400703

申请日：2013-03-14

申请人： Rajiv Gupta ,  Luis Fernando Velasquez-Garcia ,  Richard Lanza ,  Berthold K P Horn ,  Akintunde Ibitayo Akinwande

发明人： Rajiv Gupta ,  Luis Fernando Velasquez-Garcia ,  Richard Lanza ,  Berthold K P Horn ,  Akintunde Ibitayo Akinwande

IPC分类号： A61B6/00 ,  G01N23/04 ,  G01V5/00 ,  H01J35/06 ,  H01J35/12

摘要： Described here is a method for performing phase contrast imaging using an array of independently controllable x-ray sources. The array of x-ray sources can be controlled to produce a distinct spatial pattern of x-ray radiation and thus can be used to encode phase contrast signals without the need for a coded aperture. The lack of coded aperture increases the flexibility of the imaging method. For instance, because a fixed, coded aperture is not required, the angular resolution of the imaging technique can be increased as compared to coded-aperture imaging. Moreover, the lack of a radioopaque coded aperture increases the photon flux that reaches the subject, thereby increasing the attainable signal-to-noise ratio.