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1.发明授权Information processing apparatus with prefetch control for prefetching data structure from memory through cache memory 失效具有预取控制的信息处理装置，用于通过高速缓冲存储器从存储器预取数据结构
公开(公告)号：US5721865A
公开(公告)日：1998-02-24
申请号：US588503
申请日：1996-01-18
申请人： Yooichi Shintani , Yoshikazu Tanaka , Naohiko Irie , William S. Worley, Jr. , B. Ramakrishna Rau , Rajiv Gupta , Frederic C. Amerson
发明人： Yooichi Shintani , Yoshikazu Tanaka , Naohiko Irie , William S. Worley, Jr. , B. Ramakrishna Rau , Rajiv Gupta , Frederic C. Amerson
CPC分类号： G06F9/3455 , G06F9/30047 , G06F9/30181 , G06F9/383 , G06F9/3834
摘要： To improve the function of a circuit for prefetching data accessed by a processor, a prefetch unit incorporates therein a circuit for issuing a request to read out one group of data to be prefetched and registers for holding the group of data read in response to the read request therein. The group of data are read out from a cache memory or a main memory under the control of a cache request unit. A plurality of groups of data can be prefetched. When data designation is made, the processor requests the cache memory to read a block to which the data to be prefetched belongs. A circuit is also included in the prefetch unit, wherein when prefetched data is subsequently updated by the processor, its updated data is made invalid. Elements of a vector complex in structure, such as an indexed vector or the like can be also read out. It is also possible to cope with an interrupt generated within the processor.
摘要翻译： 为了改进用于预取由处理器访问的数据的电路的功能，预取单元在其中结合有用于发出读取需要预取的一组数据的请求的电路，并且用于保存响应于读取读取的数据组的寄存器 请求。 在高速缓存请求单元的控制下，从高速缓冲存储器或主存储器读出数据组。 可以预取多组数据。 当进行数据指定时，处理器请求高速缓冲存储器读取要预取的数据所属的块。 预取单元中还包括一个电路，其中当处理器随后更新预取的数据时，其更新的数据变为无效。 也可以读出结构中的向量复合体的元素，例如索引向量等。 也可以处理处理器内产生的中断。
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2.发明授权Method and system for propagating exception status in data registers and for detecting exceptions from speculative operations with non-speculative operations 失效在数据寄存器中传播异常状态的方法和系统，以及用非投机操作检测投机操作的异常
公开(公告)号：US5778219A
公开(公告)日：1998-07-07
申请号：US597784
申请日：1996-02-07
申请人： Frederic C. Amerson , Rajiv Gupta , Vinod K. Kathail , B. Ramakrishna Rau , Michael S. Schlansker , William S. Worley, Jr.
发明人： Frederic C. Amerson , Rajiv Gupta , Vinod K. Kathail , B. Ramakrishna Rau , Michael S. Schlansker , William S. Worley, Jr.
CPC分类号： G06F9/3865 , G06F9/30072 , G06F9/30181 , G06F9/3842 , G06F9/3863
摘要： A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file. If an exception is detected, then the exception is processed and one or more of the speculative operation are re-executed (in a non-speculative mode) where necessary to process the exception.
摘要翻译： 支持投机执行的方法包括将操作指定为投机或非投机性，然后推迟由投机操作产生的异常，同时立即通过非投机操作报告异常。 如果推测操作使用产生异常的推测操作的结果，则会传播该异常。 使用检查操作检测和报告延期异常，并将其合并到非推测操作中或作为单独检查操作插入。 用于支持推测执行的系统包括用于识别投机操作并推迟由这种操作产生的任何异常的功能单元。 功能单元可以通过存储指示在寄存器文件中发生错误的信息来延迟异常。 要检查延迟异常，功能单元然后读取寄存器文件。 如果检测到异常，则处理异常，并且在需要处理异常的情况下重新执行一个或多个推测操作（以非推测模式）。
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公开(公告)号：US5689653A
公开(公告)日：1997-11-18
申请号：US384308
申请日：1995-02-06
CPC分类号： G06F9/30043 , G06F15/8084 , G06F9/30036 , G06F9/3455 , G06F9/383
摘要： The op-code bandwidth limitation of computer systems is alleviated by providing one or more vector buffers. Data is transferred between memory and processor registers in a two part process using the vector buffers. In a first part, a vector request instruction initiates buffering of data by storing data in control registers identifying a set of data elements (a vector) in the memory. When the identifying information is loaded in the control registers, a vector prefetch controller transfers elements of the vector between the memory and a vector buffer. In a second part, vector element operation instructions transfer a next element of the vector between the vector buffer and a specified processor register for use in arithmetic or logic operations.
摘要翻译： 通过提供一个或多个向量缓冲器来减轻计算机系统的操作码带宽限制。 数据在存储器和处理器寄存器之间使用向量缓冲区在两部分进程中传输。 在第一部分中，向量请求指令通过将数据存储在识别存储器中的一组数据元素（矢量）的控制寄存器中来发起数据的缓冲。 当识别信息被加载到控制寄存器中时，向量预取控制器在存储器和向量缓冲器之间传送向量的元素。 在第二部分中，向量元素操作指令将矢量的下一个元素传送到矢量缓冲器和指定的处理器寄存器之间，用于算术或逻辑运算。
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4.发明授权Method and system for deferring exceptions generated during speculative execution 失效用于推迟在投机执行期间产生的异常的方法和系统
公开(公告)号：US5692169A
公开(公告)日：1997-11-25
申请号：US324940
申请日：1994-10-18
申请人： Vinod K. Kathail , Rajiv Gupta , Bantwal R. Rau , Michael S. Schlansker , William S. Worley, Jr. , Frederic C. Amerson
发明人： Vinod K. Kathail , Rajiv Gupta , Bantwal R. Rau , Michael S. Schlansker , William S. Worley, Jr. , Frederic C. Amerson
CPC分类号： G06F9/3865 , G06F9/30072 , G06F9/30181 , G06F9/30189 , G06F9/3842
摘要： A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file.
摘要翻译： 支持投机执行的方法包括将操作指定为投机或非投机性，然后推迟由投机操作产生的异常，同时立即通过非投机操作报告异常。 如果推测操作使用产生异常的推测操作的结果，则会传播该异常。 使用检查操作检测和报告延期异常，并将其合并到非推测操作中或作为单独检查操作插入。 用于支持推测执行的系统包括用于识别投机操作并推迟由这种操作产生的任何异常的功能单元。 功能单元可以通过存储指示在寄存器文件中发生错误的信息来延迟异常。 要检查延迟异常，功能单元然后读取寄存器文件。
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公开(公告)号：US5933850A
公开(公告)日：1999-08-03
申请号：US843795
申请日：1997-04-21
CPC分类号： G06F9/3808 , G06F12/0875 , G06F9/30149 , G06F9/30178 , G06F9/322 , G06F9/3802 , G06F9/3814 , G06F9/382 , G06F9/3853 , G06F9/3863
摘要： An instruction cache which separates storage cells for instruction data from storage cells for sequence control is disclosed. Instructions are decoded prior to being stored to the instruction cache which serves a primary cache, while prior hierarchical levels of memory store instructions in an encoded form. Because the instructions have a variable-length, the instruction cache includes a next address determination circuit to determine the next instruction address. The invention is advantageous because the separation of storage cells enables a next instruction address to be generated during a fetch stage for a current instruction, thereby avoiding the need for an otherwise necessary additional decoding stage. A bypass mechanism useful for any cache following a cache miss is also disclosed.
摘要翻译： 公开了一种从用于序列控制的存储单元分离用于指令数据的存储单元的指令高速缓存。 指令在被存储到服务于主缓存的指令高速缓存之前被解码，而先前的层次级别的存储器以编码形式存储指令。 由于指令具有可变长度，所以指令高速缓存包括下一个地址确定电路以确定下一个指令地址。 本发明是有利的，因为存储单元的分离使得能够在当前指令的获取阶段期间产生下一个指令地址，从而避免了对另外必需的附加解码级的需要。 还公开了对于高速缓存未命中之后的任何高速缓存有用的旁路机制。
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6.发明授权System for exception recovery using a conditional substitution instruction which inserts a replacement result in the destination of the excepting instruction 失效使用条件替换指令进行异常恢复的系统，该指令将替换结果插入到除外指令的目的地
公开(公告)号：US5596733A
公开(公告)日：1997-01-21
申请号：US361874
申请日：1994-12-22
CPC分类号： G06F9/30076 , G06F11/0721 , G06F11/0793 , G06F9/3861 , G06F9/3877
摘要： A conditional substitution instruction is provided in an instruction set of a computer system to correct exceptions occurring during run-time. The conditional substitution instruction can be executed concurrently in a pipelined computer system with a potentially excepting instruction, or simultaneously in a wide computer system. The conditional substitution instruction substitutes a default value for the result of the potentially excepting instruction if the potentially excepting instruction produces one or more specified exceptions.
摘要翻译： 在计算机系统的指令集中提供条件替换指令，以纠正在运行期间发生的异常。 条件替换指令可以在具有潜在的除外指令的流水线计算机系统中同时执行，也可以在宽计算机系统中同时执行。 如果潜在的除外指令产生一个或多个指定的异常，条件替换指令将代替潜在的除外指令的结果的默认值。
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7.发明授权Out-of-order execution using encoded dependencies between instructions in queues to determine stall values that control issurance of instructions from the queues 失效使用队列中的指令之间的编码相关性来确定停止值，从而控制排队指令的发布，从而执行乱序执行
公开(公告)号：US5941983A
公开(公告)日：1999-08-24
申请号：US881244
申请日：1997-06-24
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/3838 , G06F9/3869 , G06F9/3885
摘要： A method for executing instructions out-of-order to improve performance of a processor includes compiling the instructions of a program into separate queues along with encoded dependencies between instructions in the different queues. The processor then issues instructions from each of these queues independently, except that it enforces the encoded dependencies among instructions from different queues. If an instruction is dependent on instructions in other queues, the processor waits to issue it until the instructions on which it depends are issued. The processor includes a stall unit, comprised of a number of instruction counters for each queue, that enforces the dependencies between instructions in different queues.
摘要翻译： 用于执行无序的指令以改善处理器的性能的方法包括将程序的指令与不同队列中的指令之间的编码的依赖关系一起编译成单独的队列。 然后处理器独立地从每个这些队列发出指令，除了它强制来自不同队列的指令之间的编码依赖性。 如果指令依赖于其他队列中的指令，则处理器等待发出，直到发出依赖于其的指令。 该处理器包括一个停顿单元，包括用于每个队列的多个指令计数器，其强制在不同队列中的指令之间的依赖性。
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公开(公告)号：US07509639B2
公开(公告)日：2009-03-24
申请号：US10794995
申请日：2004-03-04
IPC分类号： G06F9/455
CPC分类号： G06F9/468 , G06F9/5077 , G06F9/545 , G06F21/53 , G06F21/575
摘要： Methods and techniques for implementing a custom execution environment (CE2) and a related loader are provided. According to one embodiment, the CE2 includes code and data sections of an application and code and data sections of a set of system services. The set of system services has direct and full control of a set of hardware resources of a computer system containing one or more processors implementing a parallel protected architecture. According to one embodiment, the system services are designed for maximum simplicity, fastest possible speed, and elimination of security vulnerabilities.
摘要翻译： 提供了实现自定义执行环境（CE2）和相关加载程序的方法和技术。 根据一个实施例，CE2包括应用程序的代码和数据部分以及一组系统服务的代码和数据部分。 该系统服务集可以直接和完全地控制包含实现并行保护架构的一个或多个处理器的计算机系统的一组硬件资源。 根据一个实施例，系统服务被设计为最大的简单性，最快的可能速度和消除安全漏洞。
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公开(公告)号：US4713755A
公开(公告)日：1987-12-15
申请号：US750381
申请日：1985-06-28
CPC分类号： G06F9/3812 , G06F12/0804 , G06F12/0837 , Y10S707/99934
摘要： Memory integrity is maintained in a system with a hierarchical memory using a set of explicit cache control instructions. The caches in the system have two status flags, a valid bit and a dirty bit, with each block of information stored. The operating system executes selected cache control instructions to ensure memory integrity whenever there is a possibility that integrity could be compromised.
摘要翻译： 在使用一组显式高速缓存控制指令的分层存储器的系统中维持存储器完整性。 系统中的缓存具有两个状态标志，一个有效位和一个脏位，每个信息块都被存储。 操作系统执行选定的缓存控制指令，以确保内存完整性，只要可能会危及完整性。
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公开(公告)号：US6161215A
公开(公告)日：2000-12-12
申请号：US144299
申请日：1998-08-31
IPC分类号： H01L21/822 , G06F1/10 , G06F17/50 , H01L23/498 , H01L23/64 , H01L27/04
CPC分类号： G06F1/10 , G06F17/5077 , H01L23/49838 , H01L23/64 , H01L2224/17181 , H01L2924/00014 , H01L2924/15173 , H01L2924/3011 , H01L2224/0401
摘要： Signal delay and skew within an integrated circuit are minimized when 1) signals are distributed to distant points of an integrated circuit via a layer of its package, and 2) traces in the package layer are etched and treated as transmission lines. As disclosed herein, a signal is driven through a first connection between an integrated circuit and an integrated circuit package layer. The signal is then distributed to one or more additional connections between the integrated circuit and the integrated circuit package layer, by means of point-to-point transmission lines formed in the integrated circuit package layer, each of the transmission lines being terminated at one or both ends by impedances which are substantially matched to the characteristic impedance of the transmission line to which they are attached. The signal is then received into the integrated circuit through the one or more additional connections between the integrated circuit and the integrated circuit package layer.
摘要翻译： 当1）信号通过其封装层分布到集成电路的远端时，集成电路内的信号延迟和偏移被最小化，2）封装层中的迹线被蚀刻并被处理为传输线。 如本文所公开的，信号通过集成电路和集成电路封装层之间的第一连接被驱动。 然后，通过形成在集成电路封装层中的点对点传输线，将信号分配到集成电路和集成电路封装层之间的一个或多个附加连接，每条传输线以一个或多个 两端的阻抗基本上与其所连接的传输线的特性阻抗相匹配。 然后，该信号通过集成电路和集成电路封装层之间的一个或多个附加连接被接收到集成电路中。
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