公开(公告)号：US20220147131A1

公开(公告)日：2022-05-12

申请号：US17094579

申请日：2020-11-10

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Gary L. Howe ,  Miles S. Wiscombe ,  Eric J. Stave

IPC: G06F1/3203 ,  G11C11/4074

Abstract: Methods, systems, and devices for power management for a memory device are described. For example, a memory device may include one or more memory dies and may be configured to operate using a first supply voltage and a second supply voltage. The first supply voltage may be associated with a first defined voltage range, and the second supply voltage may be associated with a second defined voltage range. The memory device may include a power management integrated circuit (PMIC) that is coupled with the one or more memory dies and provides the supply voltages to the one or more memory dies. The PMIC may be configured to provide, to the one or more memory dies, a first voltage that is within the first defined voltage range as the first supply voltage and a second voltage that is outside the second defined voltage range as the second supply voltage.

公开(公告)号：US11217284B2

公开(公告)日：2022-01-04

申请号：US16839893

申请日：2020-04-03

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave

IPC: G11C7/10 ,  H03K19/00 ,  G11C29/02 ,  G11C29/50 ,  H03K19/0175

Abstract: Memory devices and systems with per pin input/output termination and driver impedance calibration capabilities, and associated methods, are disclosed herein. In one embodiment, a device apparatus includes circuitry dedicated to an individual DQ pin of the device apparatus. The circuitry can be configured to (i) generate, at least in part, a voltage at the DQ pin based, at least in part, on an impedance internal to a host device electrically connected to the device apparatus and (ii) compare the voltage to a target voltage. Based, at least in part, on the comparison, the circuitry can be configured to adjust a resistance of an output driver and/or a termination circuit of the device apparatus that correspond to the DQ pin to adjust the impedance of the output driver and/or termination circuit to match an impedance associated with a corresponding input/output pin of the host device.

公开(公告)号：US20210241810A1

公开(公告)日：2021-08-05

申请号：US17164738

申请日：2021-02-01

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis ,  James S. Rehmeyer ,  Baekkyu Choi ,  Yogesh Sharma ,  Eric J. Stave ,  Brian W. Huber ,  Miles S. Wiscombe

IPC: G11C11/406

Abstract: Methods, systems, and devices for voltage adjustment based on, for example, pending refresh operations are described. A memory device may periodically perform refresh operations to refresh volatile memory cells and may at times postpone performing one or more refresh operations. A memory device may determine a quantity of pending (e.g., postponed) refresh operations, such as by determining a quantity of refresh intervals that have elapsed without receiving or executing a refresh command, among other methods. A memory device may pre-emptively adjust (or cause to be adjusted) a supply voltage associated with the memory device or memory device component based on the quantity of pending refresh operations to prepare for the current demand associated with the performing the one or more pending refresh operations. For example, the memory device may increase a supply voltage associated with one or more components to prepare for performing multiple pending refresh operations.

公开(公告)号：US11080219B1

公开(公告)日：2021-08-03

申请号：US16744091

申请日：2020-01-15

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave

IPC: G06F13/16 ,  G06F13/40 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076

Abstract: Methods, systems, and devices for addressing scheme for a memory system are described. A memory system may include a plurality of memory devices that are coupled with various command address (CA) channels via respective pins. In some examples, different pins of each memory device may be coupled with different CA channels. When the memory system receives a command to enter a memory device into a per-device addressability (PDA) mode, certain CA channels may be driven. One or more memory devices may enter the PDA mode based on certain pins of the respective memory device being biased.

公开(公告)号：US20210201970A1

公开(公告)日：2021-07-01

申请号：US17200233

申请日：2021-03-12

Applicant: Micron Technology, Inc.

Inventor： Gary Howe ,  Eric J. Stave ,  Thomas H. Kinsley ,  Matthew A. Prather

IPC: G11C7/22 ,  G11C7/10 ,  G06F13/40 ,  G11C8/10

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

公开(公告)号：US11003386B2

公开(公告)日：2021-05-11

申请号：US16015042

申请日：2018-06-21

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Thomas H. Kinsley ,  Matthew A. Prather

IPC: G06F3/06 ,  G11C7/10 ,  G11C11/4093

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication. The device may transmit, from the first portion, a signal instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The signal may be provided at an ODT I/O terminal of the first portion coupled to an ODT I/O terminal of the second portion.

公开(公告)号：US20240268131A1

公开(公告)日：2024-08-08

申请号：US18404569

申请日：2024-01-04

Applicant: Micron Technology, Inc.

Inventor： Timothy M. Hollis ,  Eric J. Stave

IPC: H10B80/00 ,  H01L25/065

CPC classification number: H10B80/00 ,  H01L25/0657 ,  H01L2225/06534 ,  H01L2225/06541

Abstract: Methods, systems, and devices for near memory photonics are described. A memory device may include an optical interface, which may include an array of optical emitters and optical receivers, to convert between electrical signaling and optical signaling. For example, a vertical stack of memory dies may be coupled with an interface component which includes the optical interface. Optical signaling may be carried over one or more optical channels to a host device, and the host device may include an optical interface to convert the optical signaling back to electrical signaling. In some examples, the interface component may be positioned above the vertical stack of memory dies. Alternatively, the interface component may be positioned below the stack of memory dies, and may extend horizontally beyond the stack of memory dies, forming a porch section. In such cases, the optical interface may be distributed across the porch section.

公开(公告)号：US12051478B2

公开(公告)日：2024-07-30

申请号：US17131383

申请日：2020-12-22

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave

IPC: G06F11/00 ,  G11C29/50

CPC classification number: G11C29/50004 ,  G11C29/50008 ,  G11C2029/5004

Abstract: Systems, apparatuses, and methods for test devices having parallel impedances to reduce measurement input impedance are disclosed. An apparatus includes a test input terminal, a measurement output terminal, a reference voltage potential node, and a parallel resistor. The test input terminal is configured to electrically connect to a signal output terminal of a signal generator. The test input terminal is configured to receive a test signal from the signal generator via the signal output terminal. The measurement output terminal electrically connects to a measurement input terminal of an electrical measurement instrument. The parallel resistor is electrically connected from the measurement output terminal to the reference voltage potential node. A system includes the apparatus and the electrical measurement instrument. A method includes providing a test signal to the test device, verifying the test signal using the electrical measurement instrument, and providing the test signal to a device under test.

公开(公告)号：US11977751B2

公开(公告)日：2024-05-07

申请号：US17494701

申请日：2021-10-05

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave

IPC: G06F3/00 ,  G06F3/06

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for on-die termination configuration for a memory device are described. In some examples, a memory device may determine a connection option from a set of connections options for which an ODT pin of the memory device is configured. Each connection option may correspond to a termination configuration for a different pin, such as a command and address (CA) pin, a clock (CK) pin, or a chip select (CS). Based on the determined connection option, the memory device may identify a respective termination option for each of the different pins, such as a first termination option for the CA pin, a second termination option for the CK pin, and a third termination option for the CS pin, and configure each of the different pins according to the respective termination option for that pin.

公开(公告)号：US20240007092A1

公开(公告)日：2024-01-04

申请号：US17852657

申请日：2022-06-29

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Tyler J. Gomm

IPC: H03K5/156 ,  G11C7/22 ,  H03K19/21 ,  H03K5/1534

CPC classification number: H03K5/1565 ,  G11C7/222 ,  H03K19/21 ,  H03K5/1534

Abstract: A device includes a clock input circuit that when in operation receives a clock signal and transmits an internal clock signal based on the clock signal. The device also includes an internal clock generator coupled to the clock input circuit to receive the internal clock signal, wherein the internal clock generator comprises clock adjustment circuitry that when in operation generates a phase controlled internal clock signal having subsequent clock edges based upon a single clock edge of the internal clock signal, wherein the phase controlled internal clock signal comprises a first frequency as a multiple of a second frequency of the internal clock signal.