公开(公告)号：US11854651B2

公开(公告)日：2023-12-26

申请号：US17677628

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Jennifer E. Taylor

IPC: G11C7/06 ,  G11C7/10 ,  H03K3/356 ,  G11C11/4091 ,  G11C11/4093

CPC classification number: G11C7/065 ,  G11C7/106 ,  G11C7/1087 ,  G11C11/4091 ,  G11C11/4093 ,  H03K3/356139

Abstract: A memory device including an interface to receive one or more clock signals and one or more data signal a dual-sensing stage dual-tail latch arranged at the interface. The dual-sensing stage dual-tail latch includes a sensing stage to sense a differential voltage between a first signal and a second signal and to provide a first differential voltage output and a second differential voltage output to a first node and a second node, respectively. The dual-sensing stage dual-tail latch includes a complimentary sensing stage arranged in parallel with the sensing stage and to sense the differential voltage between the first signal and the second signal, where a first complimentary differential output voltage and a second complimentary differential output of the complimentary sensing stage are coupled to the first node and the second node. The dual-sensing stage dual-tail latch includes a latch stage to receive the outputs from the first node and the second node.

公开(公告)号：US20230307033A1

公开(公告)日：2023-09-28

申请号：US17701950

申请日：2022-03-23

Applicant: Micron Technology, Inc.

Inventor： John E. Riley ,  Scott E. Smith ,  Jennifer E. Taylor ,  Gary L. Howe

IPC: G06F3/06 ,  G11C11/4096 ,  G11C11/4076

CPC classification number: G06F3/061 ,  G11C11/4096 ,  G11C11/4076 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0673

Abstract: Methods, apparatuses, and systems related to operations for managing the quality of an input signal received by a device and for providing feedback in real-time. A controller can provide a reference signal to the device for the input quality check. The memory can implement the input quality check by counting the number of transitions of the reference signal for a set time period and store the resulting count value(s). The memory can use the count value(s) to determine a condition or a quality for the reference signal.

公开(公告)号：US20230267971A1

公开(公告)日：2023-08-24

申请号：US17677628

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Jennifer E. Taylor

IPC: G11C7/06 ,  G11C7/10

CPC classification number: G11C7/065 ,  G11C7/106 ,  G11C7/1087 ,  G11C11/4091

Abstract: A memory device including an interface to receive one or more clock signals and one or more data signal a dual-sensing stage dual-tail latch arranged at the interface. The dual-sensing stage dual-tail latch includes a sensing stage to sense a differential voltage between a first signal and a second signal and to provide a first differential voltage output and a second differential voltage output to a first node and a second node, respectively. The dual-sensing stage dual-tail latch includes a complimentary sensing stage arranged in parallel with the sensing stage and to sense the differential voltage between the first signal and the second signal, where a first complimentary differential output voltage and a second complimentary differential output of the complimentary sensing stage are coupled to the first node and the second node. The dual-sensing stage dual-tail latch includes a latch stage to receive the outputs from the first node and the second node.

公开(公告)号：US10714156B2

公开(公告)日：2020-07-14

申请号：US16121325

申请日：2018-09-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christian N. Mohr ,  Jennifer E. Taylor ,  Vijayakrishna J. Vankayala

IPC: G11C7/00 ,  G11C7/10 ,  H03F3/45

Abstract: Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.

公开(公告)号：US20200075067A1

公开(公告)日：2020-03-05

申请号：US16121325

申请日：2018-09-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Christian N. Mohr ,  Jennifer E. Taylor ,  Vijayakrishna J. Vankayala

IPC: G11C7/10

Abstract: Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.

公开(公告)号：US20190280907A1

公开(公告)日：2019-09-12

申请号：US16425653

申请日：2019-05-29

Applicant: Micron Technology, Inc.

Inventor： Raghukiran Sreeramaneni ,  Jennifer E. Taylor

IPC: H04L25/06 ,  H04B1/16 ,  H04L25/03

Abstract: A device includes a selection circuit that is configured to generate a bias level. The device also includes a combinational circuit coupled to the selection circuit. The combinational circuit is configured to generate a distortion correction factor used offset inter-symbol interference from a data stream on a distorted bit based on the bias level to generate a correction signal. The device additionally includes a latching element coupled to the combinational circuit and configured to receive the first correction signal.

公开(公告)号：US20190215198A1

公开(公告)日：2019-07-11

申请号：US15864972

申请日：2018-01-08

Applicant: Micron Technology, Inc.

Inventor： Raghukiran Sreeramaneni ,  Jennifer E. Taylor

IPC: H04L25/06 ,  H04L25/03 ,  H04B1/16

Abstract: A device includes a selection circuit that is configured to generate a bias level. The device also includes a combinational circuit coupled to the selection circuit. The combinational circuit is configured to generate a distortion correction factor used offset inter-symbol interference from a data stream on a distorted bit based on the bias level to generate a correction signal. The device additionally includes a latching element coupled to the combinational circuit and configured to receive the first correction signal.

公开(公告)号：US20190199557A1

公开(公告)日：2019-06-27

申请号：US16289517

申请日：2019-02-28

Applicant: Micron Technology, Inc.

Inventor： Jennifer E. Taylor ,  Raghukiran Sreeramaneni

IPC: H04L25/03

Abstract: A device including an equalizer that includes a first input configured to receive an input signal, a second input configured to receive a reference signal, and a third input configured to receive an adjustment signal. The equalizer also includes a first output configured to transmit a corrected signal, wherein the corrected signal is generated based on data outputs controlled via the input signal, the reference signal, and a clock signal, wherein the data outputs are modified based on the first adjustment signal, wherein corrected signal offsets inter-symbol interference on the input signal based on a data bit received at the first input prior to reception of the input signal.

公开(公告)号：US20190096445A1

公开(公告)日：2019-03-28

申请号：US16204716

申请日：2018-11-29

Applicant: Micron Technology, Inc.

Inventor： Jennifer E. Taylor ,  Raghukiran Sreeramaneni

IPC: G11C7/02 ,  G11C7/10 ,  G11C7/20

CPC classification number: G11C7/02 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/20 ,  G11C7/222 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/107

Abstract: A device includes a combinational circuit configured to create a one or more distortion correction factors used offset inter-symbol interference from a data stream on a distorted bit. The device also includes a selection circuit coupled to the combinational circuit. The selection circuit includes a feedback pin configured to receive a control signal and an output, wherein the selection circuit is configured to select a first distortion correction factor of the one or more distortion correction factors based upon the control signal and transmit the first distortion correction factor from the output.

公开(公告)号：US20250165340A1

公开(公告)日：2025-05-22

申请号：US18901895

申请日：2024-09-30

Applicant: Micron Technology, Inc.

Inventor： Jennifer E. Taylor ,  Timothy M. Hollis ,  Eric J. Stave ,  Chulkyu Lee ,  Chris Gregory Holub

IPC: G06F11/10

Abstract: A decision counter circuit is used in a self-adaptation circuit to apply digital averaging to input signals to obtain adaptive settings of circuit parameters for a memory chip of a memory device during the operation. Individual adaptive settings of the parameters (e.g., impedance, capacitance, equalization parameters) during operation are obtained for each of the memory chips in the memory device. The self-adaptation enables equalization adjustment across temperature and voltage drift.