公开(公告)号：US20210125658A1

公开(公告)日：2021-04-29

申请号：US17139310

申请日：2020-12-31

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano

IPC: G11C11/4076 ,  H03L7/081 ,  G11C7/22

Abstract: An apparatus may include a delay line that receives a command signal and provides a delayed command signal. The apparatus may include an edge starter that provides a clock enable signal responsive, at least in part, to a change in level of the command signal. A gate circuit of the apparatus may provide a shift clock signal responsive, at least in part, to the clock enable signal. The apparatus may also include a shifter that captures and shifts the delay command signal responsive, at least in part, to the shift clock signal.

公开(公告)号：US20190181847A1

公开(公告)日：2019-06-13

申请号：US15839531

申请日：2017-12-12

Applicant: Micron Technology, Inc.

Inventor： Yasuo Satoh ,  Kazutaka Miyano

IPC: H03K5/156 ,  G11C7/22 ,  H03K3/017 ,  H03L7/081 ,  G11C7/12

CPC classification number: H03K5/1565 ,  G11C7/1018 ,  G11C7/12 ,  G11C7/222 ,  G11C11/4076 ,  H03K3/017 ,  H03L7/0812

Abstract: Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a signal line. The offset values are based on individual transition threshold voltages biases of sample circuits of the receiver circuit. The example apparatus may further include an input/output (I/O) circuit comprising a driver circuit. The driver circuit configured to receive a logic signal and the offset values and to provide an output signal to the signal line based on the logic signal and to adjust voltages of the output signal based on the offset values.

公开(公告)号：US09997220B2

公开(公告)日：2018-06-12

申请号：US15243651

申请日：2016-08-22

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano ,  Atsuko Momma

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/22 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/222 ,  G11C2207/2272

Abstract: Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that receives a first clock signal having a first frequency and provides a complementary pair of second and third clock signals having a second frequency that is half the first frequency; a first delay circuit that receives the second clock signal and provides a delayed second clock signal responsive to the second clock signal; and a second delay circuit that receives the third clock signal and provides a delayed third clock signal responsive to the third clock signal. The timing circuit receives a first signal, latches the first signal responsive to the delayed second clock signal to provide a second signal and latches the second signal responsive to either the second clock signal or the third clock signal responsive to latency information.

公开(公告)号：US11676650B2

公开(公告)日：2023-06-13

申请号：US17362822

申请日：2021-06-29

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano ,  Yasuo Satoh ,  Kenji Mae

IPC: G11C7/00 ,  G11C11/406 ,  H03L7/081

CPC classification number: G11C11/40615 ,  H03L7/0812

Abstract: A semiconductor device may include a delay locked loop (DLL) control circuit coupled to an update trigger generator and a DLL update circuit. The DLL control circuit may receive an update trigger signal and an internal refresh signal and configured to activate the DLL update circuit responsive to an update trigger in the update trigger signal and deactivate the DLL update circuit responsive to an active internal refresh signal. The DLL update circuit may perform DLL update to one or more memory cell arrays when activated and not perform DLL update to the memory cell arrays when deactivated. The DLL control circuit may reactivate the DLL update circuit once the internal refresh signal becomes inactive. In other scenarios, once the DLL update circuit is deactivated, the DLL update circuit stays deactivated until the next update trigger in the update trigger signal.

公开(公告)号：US20230076261A1

公开(公告)日：2023-03-09

申请号：US17466052

申请日：2021-09-03

Applicant: Micron Technology, Inc.

Inventor： Navya Sri Sreeram ,  Kallol Mazumder ,  Ryo Fujimaki ,  Kazutaka Miyano ,  Yutaka Uemura

IPC: G11C7/10 ,  G11C11/4096 ,  G11C7/22 ,  G11C11/4076

Abstract: Methods, apparatuses, and systems related to coordinating a set of timing-critical operations across parallel processing pipelines are described. The coordination may include selectively using (1) circuitry associated with a corresponding pipeline to generate enable signals associated with the timing critical operations when a separation between the operations corresponds to a number of pipelines or (2) circuitry associated with a non-corresponding or another pipeline when the separation is not a factor of the number of pipelines.

公开(公告)号：US10931270B2

公开(公告)日：2021-02-23

申请号：US16725102

申请日：2019-12-23

Applicant: Micron Technology, Inc.

Inventor： Yasuo Satoh ,  Kazutaka Miyano

IPC: H03K3/017 ,  H03K5/156 ,  G11C7/22 ,  H03L7/081 ,  G11C7/12 ,  G11C11/4076 ,  G11C7/10

Abstract: Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a signal line. The offset values are based on individual transition threshold voltages biases of sample circuits of the receiver circuit. The example apparatus may further include an input/output (I/O) circuit comprising a driver circuit. The driver circuit configured to receive a logic signal and the offset values and to provide an output signal to the signal line based on the logic signal and to adjust voltages of the output signal based on the offset values.

公开(公告)号：US10892002B2

公开(公告)日：2021-01-12

申请号：US16169593

申请日：2018-10-24

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano

IPC: G11C11/4076 ,  G11C7/22 ,  H03L7/081

Abstract: An apparatus may include a delay line that receives a command signal and provides a delayed command signal. The apparatus may include an edge starter that provides a clock enable signal responsive, at least in part, to a change in level of the command signal. A gate circuit of the apparatus may provide a shift clock signal responsive, at least in part, to the clock enable signal. The apparatus may also include a shifter that captures and shifts the delay command signal responsive, at least in part, to the shift clock signal.

公开(公告)号：US10755758B2

公开(公告)日：2020-08-25

申请号：US16107909

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Shuichi Ishibashi ,  Kazutaka Miyano ,  Hiroki Fujisawa

IPC: G11C7/22 ,  G11C11/4076 ,  G11C7/10 ,  G11C8/18 ,  G11C29/02 ,  G11C8/10

Abstract: Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.

公开(公告)号：US10608620B2

公开(公告)日：2020-03-31

申请号：US16012715

申请日：2018-06-19

Applicant: Micron Technology, Inc.

Inventor： Kazutaka Miyano

IPC: G11C8/00 ,  H03K5/135 ,  H03K5/133 ,  G11C8/10 ,  G11C8/18 ,  G11C7/22

Abstract: Examples described herein include command latency shifters which may include a plurality of registers arranged in a folded topology.

公开(公告)号：US20190272862A1

公开(公告)日：2019-09-05

申请号：US16419805

申请日：2019-05-22

Applicant: Micron Technology, Inc.

Inventor： Yoshiya Komatsu ,  Kazutaka Miyano ,  Atsuko Momma

IPC: G11C7/22 ,  G11C8/10

Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device through various modes of operation. A clock enable control circuit is provided to control the input of a delay locked loop circuit to provide a locked condition based on a particular type of command input and the state of various control signals to allow for multiple locking conditions and adjustments based on a length of a clock cycle of the internal clock signal.