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公开(公告)号：US20250077455A1
公开(公告)日：2025-03-06
申请号：US18951879
申请日：2024-11-19
Applicant: Micron Technology, Inc.
Inventor： Eric N. Lee , Leonid Minz , Yoav Weinberg , Ali Feiz Zarrin Ghalam , Luigi Pilolli
Abstract: Operations include determining, based on a period of time during which a logical level of the signal line is maintained at a first logical level, that a data transfer to the memory array is being suspended, determining, while the data transfer is suspended, whether the logical level of the signal line has changed from the first logical level to a second logical level, and in response to determining that the logical level of the signal line has changed from the first logical level to the second logical level, causing warm-up cycles to be performed.
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公开(公告)号：US20250069679A1
公开(公告)日：2025-02-27
申请号：US18774638
申请日：2024-07-16
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz
Abstract: A method includes determining a target total bit-error-rate (BER), calculating a target channel BER based on the target total BER, and training a channel to the calculated target channel BER by transmitting data over the channel in a loop from a physical input/output (PHY I/O) to a memory device, transmitting the test data over the channel in the loop from the memory device to the PHY I/O, wherein the data is looped from the memory device and back to the PHY I/O without being written to or road from the memory device, determining an actual channel BER based on the data transmitted to and received from the memory device, comparing the actual channel BER to the calculated target channel BER, and regulating a voltage value based on the comparison.
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公开(公告)号：US20250004962A1
公开(公告)日：2025-01-02
申请号：US18829713
申请日：2024-09-10
Applicant: Micron Technology, Inc.
Inventor： Eric N. Lee , Leonid Minz , Yoav Weinberg , Ali Feiz Zarrin Ghalam , Luigi Pilolli
Abstract: A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data transfer across an interface bus to be suspended by toggling a logical level of a control pin from a first level that activates the data transfer to a second level that suspends the data transfer, and causing the data transfer to resume by toggling the logical level of the control pin from the second level to the first level.
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公开(公告)号：US20240429904A1
公开(公告)日：2024-12-26
申请号：US18826526
申请日：2024-09-06
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Yoav Weinberg
Abstract: A plurality of flip-flops of an integrated circuit (IC) (e.g., an ASIC) are electrically connected in a predefined series. The scan input gate of any give flip-flop in the predefined series is electrically connected to one of a Q output gate or a Q-bar output gate of an adjacent flip-flop in the predefined series. A reset operation for the IC occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the IC.
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公开(公告)号：US11888318B2
公开(公告)日：2024-01-30
申请号：US17715552
申请日：2022-04-07
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Ekram H. Bhuiyan
Abstract: Sensing circuitry and clock management circuitry provide transient load management. The sensing circuitry detects a voltage, current, and/or activity associated with a system-on-chip (SoC) and determines whether the detected voltage, current, and/or activity meets a threshold. The clock management circuitry generates clocking signals for the SoC and alters a frequency of the generated clocking signals in response to the detected voltage, current, and/or activity meeting the threshold to alter an amount of power consumed by the SoC.
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Patent Agency Ranking
公开(公告)号：US11747843B1
公开(公告)日：2023-09-05
申请号：US17717638
申请日：2022-04-11
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Ekram H. Bhuiyan
Abstract: Aspects of the present disclosure are directed to voltage drop compensation for power supplies. One method includes sensing each voltage, via a voltage sensor, of a plurality of voltages from different areas of circuit components prior to the voltage reaching a voltage regulator, receiving, at a voltage manager, a sensed voltage magnitude from the voltage sensor for at least one of the plurality of voltages, receiving, at a voltage manager, data for a number of characteristics of the circuitry components, and selecting a correction voltage to be provided to the voltage regulator based on the sensed voltage magnitude from the voltage sensor for the at least one of the plurality of voltages and data for at least one of the characteristics of the circuitry components.
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公开(公告)号：US11733274B1
公开(公告)日：2023-08-22
申请号：US17705819
申请日：2022-03-28
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz , Ekram H. Bhuiyan
IPC: G01R15/08 , G01R19/165 , G01R15/00
CPC classification number: G01R19/16557 , G01R15/005 , G01R15/08
Abstract: A voltage sensing circuit includes voltage regulators, oscillator circuits, delay circuits, and a detector circuit. The detector circuit detects characteristics of signaling received from a first oscillator circuit and characteristics of signaling received from a second oscillator circuit. The detector circuit compares the detected characteristics of the signaling from the first oscillator circuit and the second oscillator circuit to determine whether the detected characteristics from the first oscillator circuit and the second oscillator circuit meet a particular criterion for providing voltage manipulation for the voltage sensing circuit.
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公开(公告)号：US20250166676A1
公开(公告)日：2025-05-22
申请号：US18946242
申请日：2024-11-13
Applicant: Micron Technology, Inc.
Inventor： Leonid Minz
Abstract: A method includes providing a first plurality of data signals and a first plurality of clock signals to a flip-flop circuit to generate a first plurality of outputs corresponding to the first plurality of data signals and the first plurality of clock signals, providing the first plurality of outputs to a first-in first-out (FIFO) device, providing a second plurality of data signals to the flip-flop circuit, providing a second plurality of clock signals generated by a controller to the flip-flop circuit, and providing a second plurality of outputs corresponding to the second plurality of data signals and the second plurality of clock signals to move the first plurality of outputs through the FIFO device.
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公开(公告)号：US20250165026A1
公开(公告)日：2025-05-22
申请号：US18949101
申请日：2024-11-15
Applicant: Micron Technology, Inc.
Inventor： Leonid Minz , Luigi Pilolli , Gyan Prakash
IPC: G06F1/06
Abstract: A method includes providing, by a controller, a plurality of control signals and a first plurality of clock signals to a memory device. In some embodiments, the first plurality of clock signals is greater than the plurality of control signals. The method can also include receiving, at the controller, a first plurality of data signals corresponding to the plurality of control signals and a second plurality of clock signals corresponding to a first portion of the first plurality of clock signals from the memory device, and receiving, at the controller, a second plurality of data signals and a third plurality of clock signals corresponding to a second portion of the first plurality of clock signals from the memory device.
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公开(公告)号：US20240322675A1
公开(公告)日：2024-09-26
申请号：US18602819
申请日：2024-03-12
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz
Abstract: A method includes supplying, via a first voltage regulator, a first supply voltage to a first voltage domain including circuitry configured to operate at the first supply voltage, supplying, via a second voltage regulator, a second supply voltage to a second voltage domain including circuitry configured to operate in a voltage zone, detecting a change in an error characteristic of data associated with the second voltage domain, and altering the second supply voltage to an altered supply voltage based on the change in the error characteristic.
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