公开(公告)号：US20220391127A1

公开(公告)日：2022-12-08

申请号：US17339660

申请日：2021-06-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tawalin Opastrakoon ,  Renato C. Padilla ,  Michael G. Miller ,  Christopher M. Smitchger ,  Gary F. Besinga ,  Sampath K. Ratnam ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06

Abstract: A plurality of host data items, including a first host data item and a second host data item, are received. The second host data item consecutively follows the first host data item. The first host data item is stored in a first page of a first logical unit of the memory device, wherein the first page is associated with a first page number. A second page number is determined for the second host data item based on an offset value that corresponds to a number of pages per wordline of the memory device. A second logical unit of the memory device is identified. The second host data item is stored in a second page of the second logical unit, wherein the second page is identified by the second page number, and the first page and the second page are associated with a fault-tolerant stripe.

公开(公告)号：US11507304B1

公开(公告)日：2022-11-22

申请号：US17339660

申请日：2021-06-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tawalin Opastrakoon ,  Renato C. Padilla ,  Michael G. Miller ,  Christopher M. Smitchger ,  Gary F. Besinga ,  Sampath K. Ratnam ,  Vamsi Pavan Rayaprolu

IPC: G06F12/00 ,  G06F3/06

Abstract: A plurality of host data items, including a first host data item and a second host data item, are received. The second host data item consecutively follows the first host data item. The first host data item is stored in a first page of a first logical unit of the memory device, wherein the first page is associated with a first page number. A second page number is determined for the second host data item based on an offset value that corresponds to a number of pages per wordline of the memory device. A second logical unit of the memory device is identified. The second host data item is stored in a second page of the second logical unit, wherein the second page is identified by the second page number, and the first page and the second page are associated with a fault-tolerant stripe.

公开(公告)号：US20220310190A1

公开(公告)日：2022-09-29

申请号：US17212531

申请日：2021-03-25

Applicant: Micron Technology, Inc.

Inventor： Gary F. Besinga ,  Renato C. Padilla ,  Tawalin Opastrakoon ,  Sampath K. Ratnam ,  Michael G. Miller ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC: G11C29/44 ,  G11C29/42 ,  G11C29/50 ,  G11C29/00 ,  G11C16/10 ,  G11C16/26

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving a set of read offsets for a block of the memory device, the set of read offsets comprising a default read offset, selecting the default read offset from the set of read offsets based on one or more criteria, applying the default read offset to a read operation performed with respect to the block, determining that a second set of criteria associated with removing the default read offset is satisfied, and removing the default read offset responsive to determining that the second set of criteria is satisfied.

公开(公告)号：US20220188226A1

公开(公告)日：2022-06-16

申请号：US17123244

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Gary F. Besinga ,  Renato C. Padilla ,  Tawalin Opastrakoon ,  Sampath K. Ratnam ,  Michael G. Miller ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC: G06F12/06 ,  G06F1/28

Abstract: An amount of threshold voltage distribution shift is determined. The threshold voltage distribution shift corresponds to an amount of time after programming of a reference page of a block of a memory device. A program-verify voltage is adjusted based on the amount of threshold voltage distribution shift to obtain an adjusted program-verify voltage. Using the adjusted program-verify voltage, a temporally subsequent page of the block is programmed at a time corresponding to the amount of time after the programming of the reference page.

公开(公告)号：US11361833B2

公开(公告)日：2022-06-14

申请号：US16690546

申请日：2019-11-21

Applicant: Micron Technology, Inc.

Inventor： Bruce A. Liikanen ,  Gerald L. Cadloni ,  Gary F. Besinga ,  Michael G. Miller ,  Renato C. Padilla

IPC: G11C16/34 ,  G11C29/52 ,  G11C16/26 ,  G11C7/18 ,  G11C8/14 ,  G11C16/04

Abstract: Several embodiments of memory devices and systems with offset memory component automatic calibration error recovery are disclosed herein. In one embodiment, a system includes at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to one or more of a plurality of offset read level test signals, including a base offset read level test signal. The base offset read level test signal is offset from the current read level signal by a predetermined value. The calibration circuitry is further configured to output the determined read level offset value.

公开(公告)号：US20220066651A1

公开(公告)日：2022-03-03

申请号：US17007559

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Gary F. Besinga

IPC: G06F3/06

Abstract: An asynchronous power loss (APL) event is detected at a memory device. An APL affected page is identified in the memory device in response to detecting the APL event. A dummy write operation is performed to write dummy data to the APL affected page using an enhanced programming sequence with a reduced pulse count to reduce program disturb errors on neighboring pages.

公开(公告)号：US11250918B2

公开(公告)日：2022-02-15

申请号：US17035149

申请日：2020-09-28

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Michael G. Miller ,  Sampath Ratnam ,  Xu Zhang ,  Jie Zhou

IPC: G06F12/00 ,  G11C16/26 ,  G06F11/10 ,  G06F11/07 ,  G06F11/22 ,  G06F12/02 ,  G11C7/06 ,  G11C16/34

Abstract: Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.

公开(公告)号：US20210365184A1

公开(公告)日：2021-11-25

申请号：US17444416

申请日：2021-08-04

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller

IPC: G06F3/06

Abstract: The occurrence of an asynchronous power loss (APL) event is detected in a memory sub-system. In response, an APL handling operation is performed. The APL handing operation includes identifying a last written page at a first page location in a block of the memory device, wherein the last written page is associated with a memory cell of the memory device, copying data from the last written page and from a related page associated with the memory cell to a temporary storage area in the memory device, copying the data from the temporary storage area to a second page location in the block of the memory device, and providing a notification that the memory device has recovered from the APL event.

公开(公告)号：US11158392B2

公开(公告)日：2021-10-26

申请号：US16412879

申请日：2019-05-15

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Ashutosh Malshe ,  Preston A. Thomson ,  Michael G. Miller ,  Gary F. Besinga ,  Scott A. Stoller ,  Sampath K. Ratnam ,  Renato C. Padilla ,  Peter Feeley

IPC: G11C16/34

Abstract: Apparatuses and methods for operating mixed mode blocks. One example method can include tracking single level cell (SLC) mode cycles and extra level cell (XLC) mode cycles performed on the mixed mode blocks, maintaining a mixed mode cycle count corresponding to the mixed mode blocks, and adjusting the mixed mode cycle count differently for mixed mode blocks operated in a SLC mode than for mixed blocks operated in a XLC mode.

公开(公告)号：US20210232508A1

公开(公告)日：2021-07-29

申请号：US17227473

申请日：2021-04-12

Applicant: Micron Technology, Inc.

Inventor： Dheeraj Srinivasan ,  Ali Mohammadzadeh ,  Michael G. Miller ,  Xiaoxiao Zhang ,  Jung Sheng Hoei

IPC: G06F12/1009 ,  G11C11/56 ,  G06F11/07 ,  G06F3/06 ,  G06F12/02

Abstract: An example method of the present disclosure includes, responsive to a loss of last written page information by a memory system, initiating a last written page search to determine last written page information of a memory device, where the last written page search is initiated via a command from a controller of the memory system to the memory device, responsive to receiving the command, performing the last written page search on the memory device, and providing the last written page information to the controller.