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公开(公告)号：US11923030B2
公开(公告)日：2024-03-05
申请号：US17888641
申请日：2022-08-16
发明人： Gary F. Besinga , Renato C. Padilla , Tawalin Opastrakoon , Sampath K. Ratnam , Michael G. Miller , Christopher M. Smitchger , Vamsi Pavan Rayaprolu , Ashutosh Malshe
CPC分类号： G11C29/44 , G11C16/10 , G11C16/26 , G11C29/42 , G11C29/50004 , G11C29/783
摘要： A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including initiating a read operation with respect to a block of the memory device, selecting, based on a set of criteria, a default read offset from a set of read offsets, wherein the set of criteria includes at least one of: a parameter related to trigger rate, or an amount of time that an open block is allowed to remain open to control threshold voltage shift due to storage charge loss, and applying the default read offset to a read operation performed with respect to the block.
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公开(公告)号：US20230393922A1
公开(公告)日：2023-12-07
申请号：US17965909
申请日：2022-10-14
发明人： Sampath K. Ratnam , Sean Brasfield , Gary F. Besinga , Michael G. Miller , Renato C. Padilla , Tawalin Opastrakoon
IPC分类号： G06F11/07
CPC分类号： G06F11/0772
摘要： Respective error handling (EH) flags can be set based at least in part on media management data of a memory device. Whether any of the EH flags are set can be determined. In response to determining that at least one of the EH flags is set, a subset of a plurality of operations of an EH flow associated with the set EH flags can be performed.
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公开(公告)号：US20220351796A1
公开(公告)日：2022-11-03
申请号：US17867538
申请日：2022-07-18
发明人： Renato C. Padilla , Sampath K. Ratnam , Christopher M. Smitchger , Vamsi Pavan Rayaprolu , Gary F. Besinga , Michael G. Miller , Tawalin Opastrakoon
摘要： A method includes associating each block of a plurality of blocks of a memory device with a corresponding frequency access group of a plurality of frequency access groups based on corresponding access frequencies, and performing scan operations on blocks of each of the plurality of frequency access groups using a scan frequency that is different from scan frequencies of other frequency access groups. A scan operation performed on a frequency access group with a higher access frequency uses a higher scan frequency than a scan operation performed on a frequency access group with a lower access frequency.
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公开(公告)号：US20220391127A1
公开(公告)日：2022-12-08
申请号：US17339660
申请日：2021-06-04
发明人： Tawalin Opastrakoon , Renato C. Padilla , Michael G. Miller , Christopher M. Smitchger , Gary F. Besinga , Sampath K. Ratnam , Vamsi Pavan Rayaprolu
IPC分类号： G06F3/06
摘要： A plurality of host data items, including a first host data item and a second host data item, are received. The second host data item consecutively follows the first host data item. The first host data item is stored in a first page of a first logical unit of the memory device, wherein the first page is associated with a first page number. A second page number is determined for the second host data item based on an offset value that corresponds to a number of pages per wordline of the memory device. A second logical unit of the memory device is identified. The second host data item is stored in a second page of the second logical unit, wherein the second page is identified by the second page number, and the first page and the second page are associated with a fault-tolerant stripe.
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公开(公告)号：US11507304B1
公开(公告)日：2022-11-22
申请号：US17339660
申请日：2021-06-04
发明人： Tawalin Opastrakoon , Renato C. Padilla , Michael G. Miller , Christopher M. Smitchger , Gary F. Besinga , Sampath K. Ratnam , Vamsi Pavan Rayaprolu
摘要： A plurality of host data items, including a first host data item and a second host data item, are received. The second host data item consecutively follows the first host data item. The first host data item is stored in a first page of a first logical unit of the memory device, wherein the first page is associated with a first page number. A second page number is determined for the second host data item based on an offset value that corresponds to a number of pages per wordline of the memory device. A second logical unit of the memory device is identified. The second host data item is stored in a second page of the second logical unit, wherein the second page is identified by the second page number, and the first page and the second page are associated with a fault-tolerant stripe.
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公开(公告)号：US20220310190A1
公开(公告)日：2022-09-29
申请号：US17212531
申请日：2021-03-25
发明人： Gary F. Besinga , Renato C. Padilla , Tawalin Opastrakoon , Sampath K. Ratnam , Michael G. Miller , Christopher M. Smitchger , Vamsi Pavan Rayaprolu , Ashutosh Malshe
摘要： A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving a set of read offsets for a block of the memory device, the set of read offsets comprising a default read offset, selecting the default read offset from the set of read offsets based on one or more criteria, applying the default read offset to a read operation performed with respect to the block, determining that a second set of criteria associated with removing the default read offset is satisfied, and removing the default read offset responsive to determining that the second set of criteria is satisfied.
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公开(公告)号：US20220188226A1
公开(公告)日：2022-06-16
申请号：US17123244
申请日：2020-12-16
发明人： Gary F. Besinga , Renato C. Padilla , Tawalin Opastrakoon , Sampath K. Ratnam , Michael G. Miller , Christopher M. Smitchger , Vamsi Pavan Rayaprolu , Ashutosh Malshe
摘要： An amount of threshold voltage distribution shift is determined. The threshold voltage distribution shift corresponds to an amount of time after programming of a reference page of a block of a memory device. A program-verify voltage is adjusted based on the amount of threshold voltage distribution shift to obtain an adjusted program-verify voltage. Using the adjusted program-verify voltage, a temporally subsequent page of the block is programmed at a time corresponding to the amount of time after the programming of the reference page.
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公开(公告)号：US12086427B2
公开(公告)日：2024-09-10
申请号：US17677641
申请日：2022-02-22
发明人： Sriteja Yamparala , Fulvio Rori , Marco Domenico Tiburzi , Walter Di Francesco , Chiara Cerafogli , Tawalin Opastrakoon
CPC分类号： G06F3/0625 , G06F1/08 , G06F1/28 , G06F3/0653 , G06F3/0673
摘要： Various embodiments of the present disclosure relate to monitoring the integrity of power signals within memory systems. A method can include receiving a power signal at a memory component, and monitoring, via a power signal monitoring component of the memory component, an integrity characteristic of the power signal. Responsive to the integrity characteristic meeting a particular criteria, the method can include providing a status indication to a control component external to the memory component.
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公开(公告)号：US11715541B2
公开(公告)日：2023-08-01
申请号：US17867538
申请日：2022-07-18
发明人： Renato C. Padilla , Sampath K. Ratnam , Christopher M. Smitchger , Vamsi Pavan Rayaprolu , Gary F. Besinga , Michael G. Miller , Tawalin Opastrakoon
CPC分类号： G11C29/10 , G06F11/076 , G06F11/0736 , G06F11/0757 , G06F11/1048 , G11C29/52
摘要： A method includes associating each block of a plurality of blocks of a memory device with a corresponding frequency access group of a plurality of frequency access groups based on corresponding access frequencies, and performing scan operations on blocks of each of the plurality of frequency access groups using a scan frequency that is different from scan frequencies of other frequency access groups. A scan operation performed on a frequency access group with a higher access frequency uses a higher scan frequency than a scan operation performed on a frequency access group with a lower access frequency.
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公开(公告)号：US11456051B1
公开(公告)日：2022-09-27
申请号：US17212531
申请日：2021-03-25
发明人： Gary F. Besinga , Renato C. Padilla , Tawalin Opastrakoon , Sampath K. Ratnam , Michael G. Miller , Christopher M. Smitchger , Vamsi Pavan Rayaprolu , Ashutosh Malshe
摘要： A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving a set of read offsets for a block of the memory device, the set of read offsets comprising a default read offset, selecting the default read offset from the set of read offsets based on one or more criteria, applying the default read offset to a read operation performed with respect to the block, determining that a second set of criteria associated with removing the default read offset is satisfied, and removing the default read offset responsive to determining that the second set of criteria is satisfied.
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