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公开(公告)号：US10475488B1
公开(公告)日：2019-11-12
申请号：US15975713
申请日：2018-05-09
Applicant: Micron Technology, Inc.
Inventor： Scott E. Smith , Vijayakrishna J. Vankayala
IPC: G11C7/10 , G11C11/4093 , G11C11/408 , G11C7/22
Abstract: A memory device includes: a set of input pads configured to receive from a source external to the memory device one or more input signals and a chip select signal; an operation circuit electrically coupled to the input pads, operation circuit configured to perform operations corresponding to the one or more input signals when the chip select signal is enabled; and an input management circuit electrically coupled to and between the input pads and the operation circuit, the input management circuit configured to control propagation of the one or more input signals based on the chip select signal.
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公开(公告)号：US10373654B1
公开(公告)日：2019-08-06
申请号：US15976737
申请日：2018-05-10
Applicant: Micron Technology, Inc.
Inventor： Vijayakrishna J. Vankayala , Liang Chen
IPC: G11C5/02 , G11C5/06 , H01L23/48 , H01L25/065
Abstract: A memory device includes a first die configured to: generate a segment set based on a source data, wherein: the source data is information corresponding to a device operation, the source data having a block length representing a number of bits therein, the segment set including at least a first segment and a second segment, the first segment and the second segment having a number of bits less than the block length, and communicate the segment set with the second die; a second die configured to process the segment set according to the device operation; and a set of inter-die connectors electrically coupling the first die and the second die, the inter-die connectors include a number of dedicated Through-Silicon-Vias (TSVs), wherein the number is less than the block length.
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23.发明授权公开(公告)号：US12261613B2
公开(公告)日：2025-03-25
申请号：US18607999
申请日：2024-03-18
Applicant: Micron Technology, Inc.
Inventor： Vijayakrishna J. Vankayala
Abstract: A memory device includes a clock input configured to receive a clock from a host device. The memory device also includes a command input configured to receive command and address bits from the host device. The memory device further includes multiple die stacked in a three-dimensional stack. A first die of the plurality of die includes a first plurality of memory cells and first local control circuitry. The first local circuitry includes division circuitry configured to receive the clock from the clock input, generate a divided clock having a lower frequency than that of the clock, and generate multiple clocks from the divided clock with each of the multiple clocks having a lower frequency than the divided clock. The memory device also includes one or more transmitters configured to transmit the multiple clocks using inter-die interconnects between the multiple die.
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公开(公告)号：US20230335192A1
公开(公告)日：2023-10-19
申请号：US17723673
申请日：2022-04-19
Applicant: Micron Technology, Inc.
Inventor： Vijayakrishna J. Vankayala , Hari Giduturi , Jason M. Brown
IPC: G11C13/00 , H01L25/065 , G11C11/16
CPC classification number: G11C13/0061 , H01L25/0657 , G11C11/1693 , H01L2225/06506 , H01L2225/06541
Abstract: A memory device includes a substrate with two or more memory die stacked in a three-dimensional stacked (3DS) configuration. The memory device includes a clock input configured to receive a clock from a host device. The memory device also includes a command input configured to receive command and address bits from the host device. The two or more memory die each include its own plurality of memory cells. Furthermore, each of the two or more memory die include a local control circuitry configured to receive or transmit a divided clock that is based on the clock.
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公开(公告)号：US11380395B2
公开(公告)日：2022-07-05
申请号：US17013234
申请日：2020-09-04
Applicant: Micron Technology, Inc.
Inventor： Jason M. Brown , Vijayakrishna J. Vankayala
Abstract: Memory devices may have a memory array and a delay locked loop (DLL) circuit that adjusts signals associated with operations to access of the memory array. The memory device may also include a controller that delays an access command to access the memory array by transmitting the access command through delay circuitry of the DLL circuit. This may cause the access command to be delayed by a first duration of time when output from the delay circuitry. Delay of the access command may align a data signal and the access command such that the access command and a system clock may cause latching of suitable data of the data signal.
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Patent Agency Ranking
公开(公告)号：US11334426B2
公开(公告)日：2022-05-17
申请号：US16853479
申请日：2020-04-20
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Thanh K. Mai , Vijayakrishna J. Vankayala
Abstract: A memory device includes cyclic redundancy check (CRC) circuitry configured to indicate whether an error has been detected in transmission of data from a host device to the memory device. The CRC circuitry includes a synchronous counter that is configured to synchronize a count with a system clock and to transmit the count. The CRC circuitry also includes pulse width control circuitry that is configured to receive the synchronized count from the synchronous counter and to generate pulse width controls based at least in part on the synchronized count. Furthermore, the CRC circuitry includes synchronization circuitry that is configured to receive the pulse width controls and to generate an error alert signal based at least in part on the pulse width controls.
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公开(公告)号：US20220076745A1
公开(公告)日：2022-03-10
申请号：US17013234
申请日：2020-09-04
Applicant: Micron Technology, Inc.
Inventor： Jason M. Brown , Vijayakrishna J. Vankayala
Abstract: Memory devices may have a memory array and a delay locked loop (DLL) circuit that adjusts signals associated with operations to access of the memory array. The memory device may also include a controller that delays an access command to access the memory array by transmitting the access command through delay circuitry of the DLL circuit. This may cause the access command to be delayed by a first duration of time when output from the delay circuitry. Delay of the access command may align a data signal and the access command such that the access command and a system clock may cause latching of suitable data of the data signal.
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公开(公告)号：US20210326200A1
公开(公告)日：2021-10-21
申请号：US16853479
申请日：2020-04-20
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Thanh K. Mai , Vijayakrishna J. Vankayala
Abstract: A memory device includes cyclic redundancy check (CRC) circuitry configured to indicate whether an error has been detected in transmission of data from a host device to the memory device. The CRC circuitry includes a synchronous counter that is configured to synchronize a count with a system clock and to transmit the count. The CRC circuitry also includes pulse width control circuitry that is configured to receive the synchronized count from the synchronous counter and to generate pulse width controls based at least in part on the synchronized count. Furthermore, the CRC circuitry includes synchronization circuitry that is configured to receive the pulse width controls and to generate an error alert signal based at least in part on the pulse width controls.
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公开(公告)号：US10770116B2
公开(公告)日：2020-09-08
申请号：US16446876
申请日：2019-06-20
Applicant: Micron Technology, Inc.
Inventor： Vijayakrishna J. Vankayala , Liang Chen
IPC: G11C5/02 , G11C5/06 , H01L23/48 , H01L25/065 , G11C7/10
Abstract: A memory device includes active circuitry configured to process a segment set that corresponds to a source data, wherein: the source data comprises information corresponding to a device operation, the source data having a block length representing a number of bits therein, and the segment set includes at least a first segment and a second segment, the first segment and the second segment each including number of bits less than the block length; and a set of die pads coupled to the active circuitry and configured to communicate the segment set for operating a second device, wherein the set includes a number of die pads less than the block length.
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公开(公告)号：US10714156B2
公开(公告)日：2020-07-14
申请号：US16121325
申请日：2018-09-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Christian N. Mohr , Jennifer E. Taylor , Vijayakrishna J. Vankayala
Abstract: Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.
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