公开(公告)号：US10387046B2

公开(公告)日：2019-08-20

申请号：US15189900

申请日：2016-06-22

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Gary L. Howe ,  Daniel B. Penney

IPC: G11C8/00 ,  G06F3/06 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.

公开(公告)号：US20190066790A1

公开(公告)日：2019-02-28

申请号：US16110992

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Gary L. Howe

IPC: G11C16/08 ,  G11C11/16 ,  G11C11/406

CPC classification number: G11C16/08 ,  G11C5/063 ,  G11C7/1045 ,  G11C11/161 ,  G11C11/40603 ,  G11C11/4076 ,  G11C11/408 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008

Abstract: A semiconductor device may include a plurality of memory banks, a plurality of mode registers that may control an operational mode associated with each of the plurality of memory banks, and a set of global wiring lines coupled to each of the plurality of mode registers. The set of global wiring lines may include a first global wiring line to transmit data to each of the plurality of mode registers, a second global wiring line to transmit an address signal to each of the plurality of mode registers, a third global wiring line to transmit a read command signal to each of the plurality of mode registers, and a fourth global wiring line to transmit a write command signal to each of the plurality of mode registers.

公开(公告)号：US20230393929A1

公开(公告)日：2023-12-07

申请号：US17829576

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Parthasarathy Gajapathy ,  David R. Brown

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0673

Abstract: A memory device includes a command interface that when operating receives a write command, an input output interface that when in operation receives data signals in conjunction with the write command, and error detection circuitry coupled to the input output interface. The error detection circuitry is configured to generate a first signal indicative of a first period of time during which a first determination is made regarding a first portion of the data signals utilizing a first data strobe signal as a first clock signal, generate a second signal indicative of a second period of time during which a second determination is made regarding a second portion of the data signals utilizing a second data strobe signal as a second clock signal, and generate a control signal based upon the first signal, the second signal, and a slower of the first data strobe signal and the second data strobe signal.

公开(公告)号：US10929023B2

公开(公告)日：2021-02-23

申请号：US16541764

申请日：2019-08-15

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Gary L. Howe ,  Daniel B. Penney

IPC: G06F3/06 ,  G11C8/00 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.

公开(公告)号：US11755206B2

公开(公告)日：2023-09-12

申请号：US17178889

申请日：2021-02-18

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Gary L. Howe ,  Daniel B. Penney

IPC: G06F3/06 ,  G11C8/00 ,  G06F13/16

CPC classification number: G06F3/061 ,  G06F3/0625 ,  G06F3/0646 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/161 ,  G11C8/00 ,  Y02D10/00

Abstract: The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.

公开(公告)号：US10068648B1

公开(公告)日：2018-09-04

申请号：US15691217

申请日：2017-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Thanh K. Mai ,  Gary Howe

IPC: G11C7/00 ,  G11C16/08 ,  G11C11/406 ,  G11C11/16

Abstract: A semiconductor device may include a plurality of memory banks, a plurality of mode registers that may control an operational mode associated with each of the plurality of memory banks, and a set of global wiring lines coupled to each of the plurality of mode registers. The set of global wiring lines may include a first global wiring line to transmit data to each of the plurality of mode registers, a second global wiring line to transmit an address signal to each of the plurality of mode registers, a third global wiring line to transmit a read command signal to each of the plurality of mode registers, and a fourth global wiring line to transmit a write command signal to each of the plurality of mode registers.

公开(公告)号：US12019512B2

公开(公告)日：2024-06-25

申请号：US17829576

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Parthasarathy Gajapathy ,  David R. Brown

IPC: G06F11/10

CPC classification number: G06F11/1004

Abstract: A memory device includes a command interface that when operating receives a write command, an input output interface that when in operation receives data signals in conjunction with the write command, and error detection circuitry coupled to the input output interface. The error detection circuitry is configured to generate a first signal indicative of a first period of time during which a first determination is made regarding a first portion of the data signals utilizing a first data strobe signal as a first clock signal, generate a second signal indicative of a second period of time during which a second determination is made regarding a second portion of the data signals utilizing a second data strobe signal as a second clock signal, and generate a control signal based upon the first signal, the second signal, and a slower of the first data strobe signal and the second data strobe signal.

公开(公告)号：US11334426B2

公开(公告)日：2022-05-17

申请号：US16853479

申请日：2020-04-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Thanh K. Mai ,  Vijayakrishna J. Vankayala

IPC: G06F11/10 ,  G06F11/16 ,  G06F11/07

Abstract: A memory device includes cyclic redundancy check (CRC) circuitry configured to indicate whether an error has been detected in transmission of data from a host device to the memory device. The CRC circuitry includes a synchronous counter that is configured to synchronize a count with a system clock and to transmit the count. The CRC circuitry also includes pulse width control circuitry that is configured to receive the synchronized count from the synchronous counter and to generate pulse width controls based at least in part on the synchronized count. Furthermore, the CRC circuitry includes synchronization circuitry that is configured to receive the pulse width controls and to generate an error alert signal based at least in part on the pulse width controls.

公开(公告)号：US20210326200A1

公开(公告)日：2021-10-21

申请号：US16853479

申请日：2020-04-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Thanh K. Mai ,  Vijayakrishna J. Vankayala

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/16

Abstract: A memory device includes cyclic redundancy check (CRC) circuitry configured to indicate whether an error has been detected in transmission of data from a host device to the memory device. The CRC circuitry includes a synchronous counter that is configured to synchronize a count with a system clock and to transmit the count. The CRC circuitry also includes pulse width control circuitry that is configured to receive the synchronized count from the synchronous counter and to generate pulse width controls based at least in part on the synchronized count. Furthermore, the CRC circuitry includes synchronization circuitry that is configured to receive the pulse width controls and to generate an error alert signal based at least in part on the pulse width controls.

公开(公告)号：US20210173557A1

公开(公告)日：2021-06-10

申请号：US17178889

申请日：2021-02-18

Applicant: Micron Technology, Inc.

Inventor： Thanh K. Mai ,  Gary L. Howe ,  Daniel B. Penney

IPC: G06F3/06 ,  G11C8/00 ,  G06F13/16

Abstract: The present disclosure includes apparatuses and methods to transfer data between banks of memory cells. An example includes a plurality of banks of memory cells and a controller coupled to the plurality of subarrays configured to cause transfer of data between the plurality of banks of memory cells via internal data path operations.