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公开(公告)号：US12062401B2
公开(公告)日：2024-08-13
申请号：US17892437
申请日：2022-08-22
Applicant: Micron Technology, Inc.
Inventor： Wei Wang , Seungjune Jeon , Yang Liu , Charles See Yeung Kwong
CPC classification number: G11C16/3431 , G11C16/0483
Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a data integrity check on a set of memory cells of a source management unit of the memory device to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a first threshold; responsive to determining that the data integrity metric value fails to satisfy the first threshold, determining whether the data integrity metric value satisfies a second threshold that is lower than the first threshold; responsive to determining that the data integrity metric value satisfies the second threshold, causing the memory device to copy data from the source management unit to a destination set of pages of the memory device; and performing a subsequent data integrity check on one or more invalid pages of the source management unit.
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公开(公告)号：US11994945B2
公开(公告)日：2024-05-28
申请号：US18296595
申请日：2023-04-06
Applicant: Micron Technology, Inc.
Inventor： Zhenming Zhou , Tingjun Xie , Charles See Yeung Kwong
CPC classification number: G06F11/106 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F11/1068
Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, determining that a value of a write counter associated with the memory device satisfies a first threshold criterion, wherein the write counter is a global counter indicating a number of write operations to the memory device. The operations performed by the processing device further include determining that a set of failed bit count statistics corresponding to a plurality of codewords of a memory unit satisfies a second threshold criterion. The operations performed by the processing device further include, responsive to determining that the set of failed bit count statistics corresponding to the plurality of codewords of the memory unit satisfies the second threshold criterion, performing a write scrub operation on the memory unit.
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公开(公告)号：US11989107B2
公开(公告)日：2024-05-21
申请号：US17860289
申请日：2022-07-08
Applicant: Micron Technology, Inc.
Inventor： Tingjun Xie , Charles See Yeung Kwong
CPC classification number: G06F11/2094 , G06F3/0619 , G06F3/0659 , G06F3/0673
Abstract: A system includes a memory device having a plurality of memory dies and at least a first spare memory die and a processing device coupled to the memory device. The processing device is to perform operations including: tracking a value of a write counter representing a number of write operations performed at the plurality of memory dies; activating the first spare memory die in response to detecting a failure of a first memory die of the plurality of memory dies; storing an offset value of the write counter in response to activating the first spare memory die; and commanding the memory device to modify die trim settings of the first spare memory die at predetermined check point values of the write counter that are offset from the offset value.
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公开(公告)号：US20240145010A1
公开(公告)日：2024-05-02
申请号：US18404827
申请日：2024-01-04
Applicant: Micron Technology, Inc.
Inventor： Zhongguang Xu , Nicola Ciocchini , Zhenlei Shen , Charles See Yeung Kwong , Murong Lang , Ugo Russo , Niccolo' Righetti
CPC classification number: G11C16/102 , G11C16/08 , G11C16/26 , G11C16/3481
Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.
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公开(公告)号：US20230402108A1
公开(公告)日：2023-12-14
申请号：US18238850
申请日：2023-08-28
Applicant: Micron Technology, Inc.
Inventor： Tingjun Xie , Zhenming Zhou , Zhenlei Shen , Charles See Yeung Kwong
CPC classification number: G11C16/3418 , G11C16/24 , G11C16/08 , G11C16/102 , G11C16/26
Abstract: It is determined whether a write disturb capability associated with a first location of a memory device satisfies a threshold criterion. Responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, a plurality of memory units is remapped to a second location of the memory device, wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion.
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Patent Agency Ranking
公开(公告)号：US20230393920A1
公开(公告)日：2023-12-07
申请号：US17858731
申请日：2022-07-06
Applicant: Micron Technology, Inc.
Inventor： Charles See Yeung Kwong , Seungjune Jeon , Wei Wang , Zhenming Zhou
CPC classification number: G06F11/076 , G06F11/073 , G06F11/008
Abstract: A set of blocks of a memory device comprising a plurality of dies is identified. A block within the set of blocks is identified. The identified block is associated with a capability metric that reflects a projected reliability of the die on which the block resides. Responsive to determining that the capability metric satisfies a condition, a cycle threshold associated with the die is identified. Responsive to determining that a cycle count value derived from a program/erase cycle counter associated with the die matches the cycle threshold, the set of blocks is updated by excluding the block from the set of blocks. A program operation is performed with respect to the updated set of blocks.
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公开(公告)号：US11694017B2
公开(公告)日：2023-07-04
申请号：US16930158
申请日：2020-07-15
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Zhenlei Shen , Tingjun Xie , Charles See Yeung Kwong
IPC: G06F30/00 , G06F30/398 , G06F30/392 , G06F11/30 , G06F119/08
CPC classification number: G06F30/398 , G06F11/3058 , G06F30/392 , G06F2119/08
Abstract: A quality rating for a memory device to be installed at a memory sub-system is determined, where the quality rating corresponds to a performance of the memory device at one or more operating temperatures. A determination is made whether the quality rating for the memory device satisfies a first quality rating condition associated with a first temperature zone of two or more temperature zones of the memory sub-system. Responsive to the determination that the quality rating for the memory device satisfies the first quality rating condition, the memory device is assigned to be installed at a first memory device socket of the first temperature zone.
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公开(公告)号：US11656936B2
公开(公告)日：2023-05-23
申请号：US17467826
申请日：2021-09-07
Applicant: Micron Technology, Inc.
Inventor： Zhenming Zhou , Tingjun Xie , Charles See Yeung Kwong
CPC classification number: G06F11/106 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G06F11/1068
Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, determining that a value of a write counter associated with the memory device satisfies a first threshold criterion. The operations performed by the processing device further include, responsive to determining that the value of the write counter satisfies the first threshold criterion, identifying a first memory unit and a second memory unit of the memory device, the second memory unit comprising one or more memory cells adjacent to one or more memory cells of the first memory unit. The operations performed by the processing device further include performing a read operation on the second memory unit to determine a set of failed bit count statistics corresponding to a plurality of codewords of the second memory unit. The operations performed by the processing device further include determining that the set of failed bit count statistics corresponding to the plurality of codewords of the second memory unit satisfies a second threshold criterion. The operations performed by the processing device further include, responsive to determining that the set of failed bit count statistics corresponding to the plurality of codewords of the second memory unit satisfies the second threshold criterion, performing a write scrub operation on the second memory unit.
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公开(公告)号：US20230067639A1
公开(公告)日：2023-03-02
申请号：US17411278
申请日：2021-08-25
Applicant: Micron Technology, Inc.
Inventor： Tingjun Xie , Zhenming Zhou , Zhenlei Shen , Charles See Yeung Kwong
Abstract: A plurality of memory units residing in a first location of a memory device is identified, wherein the first location of the memory device corresponds to a first layer of a plurality of layers of the memory device. It is determined whether a write disturb capability associated with the first location of the memory device satisfies a threshold criterion. Responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, a plurality of logical addresses associated with the plurality of memory units is remapped to a second location of the memory device, wherein the second location of the memory device corresponds to a second layer of the plurality of layers of the memory device, and wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion.
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公开(公告)号：US20220342784A1
公开(公告)日：2022-10-27
申请号：US17860289
申请日：2022-07-08
Applicant: Micron Technology, Inc.
Inventor： Tingjun Xie , Charles See Yeung Kwong
Abstract: A system includes a memory device having a plurality of memory dies and at least a first spare memory die and a processing device coupled to the memory device. The processing device is to perform operations including: tracking a value of a write counter representing a number of write operations performed at the plurality of memory dies; activating the first spare memory die in response to detecting a failure of a first memory die of the plurality of memory dies; storing an offset value of the write counter in response to activating the first spare memory die; and commanding the memory device to modify die trim settings of the first spare memory die at predetermined check point values of the write counter that are offset from the offset value.
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