公开(公告)号：US20210057433A1

公开(公告)日：2021-02-25

申请号：US16545375

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Xiaosong Zhang ,  Yi Hu ,  Tom J. John ,  Wei Yeeng Ng ,  Chandra Tiwari

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L21/311 ,  H01L27/11565

Abstract: In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.

公开(公告)号：US10818681B2

公开(公告)日：2020-10-27

申请号：US16160342

申请日：2018-10-15

Applicant: Micron Technology Inc.

Inventor： Yi Hu ,  Jian Li ,  Lifang Xu ,  Xiaosong Zhang

IPC: H01L27/11565 ,  H01L21/768 ,  H01L27/11582

Abstract: In an example, a method of forming a stacked memory array includes, forming a termination structure passing through a stack of alternating first and second dielectrics in a first region of the stack; forming first and second sets of contacts through the stack of alternating first and second dielectrics in a second region of the stack concurrently with forming the termination structure; forming an opening through the stack of alternating first and second dielectrics between the first and second sets of contacts so that the opening terminates at the termination structure; and removing the first dielectrics from the second region by accessing the first dielectrics through the opening so that the first and second sets of contacts pass through the second dielectrics alternating with spaces corresponding to the removed first dielectrics.

公开(公告)号：US20200073257A1

公开(公告)日：2020-03-05

申请号：US16122062

申请日：2018-09-05

Applicant: Micron Technology, Inc.

Inventor： Nikolay A. Mirin ,  Robert Dembi ,  Richard T. Housley ,  Xiaosong Zhang ,  Jonathan D. Harms ,  Stephen J. Kramer

IPC: G03F7/20 ,  H01L21/68 ,  H01L23/544 ,  G01R33/07

Abstract: A method of aligning a wafer for semiconductor fabrication processes may include applying a magnetic field to a wafer, detecting one or more residual magnetic fields from one or more alignment markers within the wafer, responsive to the detected one or more residual magnetic fields, determining locations of the one or more alignment markers. The marker locations may be determined relative to an ideal grid, followed by determining a geometrical transformation model for aligning the wafer, and aligning the wafer responsive to the geometrical transformation model. Related methods and systems are also disclosed.

公开(公告)号：US20250167130A1

公开(公告)日：2025-05-22

申请号：US19030527

申请日：2025-01-17

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Harsh Narendrakumar Jain ,  John D. Hopkins ,  Xiaosong Zhang

IPC: H01L23/544

Abstract: An electronic device comprising a multideck structure including a base stack of materials and one or more stacks of materials on the base stack of materials, at least one high aspect ratio feature in an array region in the base stack of materials and in the one or more stacks of materials, and overlay marks including an optical contrast material in or on only an upper portion of the base stack of materials in an overlay mark region of the electronic device is disclosed. The overlay mark region is laterally adjacent to the array region and the overlay marks are adjacent to at least one additional high aspect ratio feature in the base stack of materials. Additional electronic devices and memory devices are disclosed.

公开(公告)号：US20250120085A1

公开(公告)日：2025-04-10

申请号：US18985534

申请日：2024-12-18

Applicant: Micron Technology, Inc.

Inventor： Md Zakir Ullah ,  Xiaosong Zhang ,  Adam L. Olson ,  Mohammad Moydul Islam ,  Tien Minh Quan Tran ,  Chao Zhu ,  Zhigang Yang ,  Merri L. Carlson ,  Hui Chin Chong ,  David A. Kewley ,  Kok Siak Tang

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. First and second arrays of pillars extend through the stack structure of the lower and upper decks, respectively. In one or more of the first and second pillar arrays, at least some pillars exhibit a greater degree of bending away from a vertical orientation than at least some other pillars. The pillars of the first array align with the pillars of the second array along an interface between the lower and upper decks. Related methods are also disclosed.

公开(公告)号：US12230546B2

公开(公告)日：2025-02-18

申请号：US17644414

申请日：2021-12-15

Applicant: Micron Technology, Inc.

Inventor： Nikolay A. Mirin ,  Robert Dembi ,  Richard T. Housley ,  Xiaosong Zhang ,  Jonathan D. Harms ,  Stephen J. Kramer

IPC: H01L21/66 ,  G03F7/00 ,  H01L21/302 ,  H01L21/68 ,  H01L23/544

Abstract: A method for measuring overlay between an interest level and a reference level of a wafer includes applying a magnetic field to a wafer, detecting at least one residual magnetic field emitted from at least one registration marker of a first set of registration markers within the wafer, responsive to the detected one or more residual magnetic fields, determining a location of the at least one registration marker of the first set registration markers, determining a location of at least one registration marker of a second set of registration markers, and responsive to the respective determined locations of the at least one registration marker of the first set of registration markers and the at least one registration marker of the second set of registration markers, calculating a positional offset between an interest level of the wafer and a reference level of the wafer. Related methods and systems are also disclosed.

公开(公告)号：US11990367B2

公开(公告)日：2024-05-21

申请号：US17444948

申请日：2021-08-12

Applicant: Micron Technology, Inc.

Inventor： Xiaosong Zhang ,  Yongjun J. Hu ,  David A. Kewley ,  Md Zahid Hossain ,  Michael J. Irwin ,  Daniel Billingsley ,  Suresh Ramarajan ,  Robert J. Hanson ,  Biow Hiem Ong ,  Keen Wah Chow

IPC: H01L21/768

CPC classification number: H01L21/76831 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76804

Abstract: An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.

公开(公告)号：US20230165004A1

公开(公告)日：2023-05-25

申请号：US18158576

申请日：2023-01-24

Applicant: Micron Technology, Inc.

Inventor： Md Zakir Ullah ,  Xiaosong Zhang ,  Adam L. Olson ,  Mohammad Moydul Islam ,  Tien Minh Quan Tran ,  Chao Zhu ,  Zhigang Yang ,  Merri L. Carlson ,  Hui Chin Chong ,  David A. Kewley ,  Kok Siak Tang

IPC: H10B43/27 ,  H10B41/27

CPC classification number: H10B43/27 ,  H10B41/27

Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. First and second arrays of pillars extend through the stack structure of the lower and upper decks, respectively. In one or more of the first and second pillar arrays, at least some pillars exhibit a greater degree of bending away from a vertical orientation than at least some other pillars. The pillars of the first array align with the pillars of the second array along an interface between the lower and upper decks. Related methods are also disclosed.

公开(公告)号：US11581264B2

公开(公告)日：2023-02-14

申请号：US16546759

申请日：2019-08-21

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Harsh Narendrakumar Jain ,  John D. Hopkins ,  Xiaosong Zhang

IPC: H01L23/544

Abstract: An electronic device comprising at least one high aspect ratio feature in a base stack of materials, overlay marks in or on only an upper portion of the base stack of materials, and an additional stack of materials adjacent the base stack of materials, the additional stack of materials comprising the at least one high aspect ratio feature. Additional electronic devices and memory devices are disclosed, as are methods of forming high aspect ratio features in an electronic device.

公开(公告)号：US20220077177A1

公开(公告)日：2022-03-10

申请号：US17016002

申请日：2020-09-09

Applicant: Micron Technology, Inc.

Inventor： Md Zakir Ullah ,  Xiaosong Zhang ,  Adam L. Olson ,  Mohammad Moydul Islam ,  Tien Minh Quan Tran ,  Chao Zhu ,  Zhigang Yang ,  Merri L. Carlson ,  Hui Chin Chong ,  David A. Kewley ,  Kok Siak Tang

IPC: H01L27/11582 ,  H01L27/11556

Abstract: Microelectronic devices include a lower deck and an upper deck, each comprising a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A lower array of pillars extends through the stack structure of the lower deck, and an upper array of pillars extends through the stack structure of the upper deck. Along an interface between the lower deck and the upper deck, the pillars of the lower array align with the pillars of the upper array. At least at elevations comprising bases of the pillars, a pillar density of the pillars of the lower array differs from a pillar density of the pillars of the upper array, “pillar density” being a number of pillars per unit of horizontal area of the respective array. Related methods and electronic systems are also disclosed.