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21.发明授权Communications processor employing line-dedicated memory tables for supervising data transfers 失效通信处理器采用行专用存储表来监控数据传输
公开(公告)号：US4261033A
公开(公告)日：1981-04-07
申请号：US760782
申请日：1977-01-19
CPC分类号： G06F13/34 , G06F13/385
摘要： A communications processor is coupled between a main memory and a plurality of communications channels and with a central processing unit and includes control mechanisms for processing the transfer of information between the processor and the main memory with minimum interruption of the central processing unit. The processor further includes control tables and a plurality of control routines enabling the processing of the transfer of the information between the processor and the channels. The routines are unique to the communications channel characteristics of the device coupled with the channel being serviced and is configurable to reflect any changes made in such characteristics.
摘要翻译： 通信处理器耦合在主存储器和多个通信信道之间并且与中央处理单元相连，并且包括用于在中央处理单元的中断最小的情况下处理处理器和主存储器之间的信息传送的控制机制。 处理器还包括控制表和多个控制例程，使得能够处理处理器和通道之间的信息传送。 这些例程对于与被维护的信道耦合的设备的通信信道特性是唯一的，并且可配置为反映在这些特性中所做的任何改变。
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公开(公告)号：US4236203A
公开(公告)日：1980-11-25
申请号：US867270
申请日：1978-01-05
CPC分类号： G06F13/368 , G06F13/4213
摘要： In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred by the highest priority requesting unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a multiple fetch operation in which the master unit requesting multiple words of information from the slave unit during a first bus transfer cycle may receive such information from the slave unit during a series of later slave generated bus cycles. Logic is provided for enabling any other units to communicate over the common bus during the time between the first cycle and such last cycle during which the slave unit responds, thereby enabling at least two pairs of units to communicate with each other respectively, in an interleaved manner.
摘要翻译： 在包括公共总线的系统中，诸如数据处理系统的用于传送信息的多个单元连接到该公共总线，在异步生成的总线传送周期期间，信息可以由最高优先级请求单元传送。 逻辑被提供用于实现多次提取操作，其中主单元在第一总线传送周期期间从从单元请求多个信息字可以在一系列随后从站产生的总线周期期间从从单元接收这些信息。 逻辑被提供用于使得任何其他单元能够在第一周期与从单元响应的最后周期之间的时间内通过公共总线进行通信，从而使得至少两对单元能够分别在交织的 方式。
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23.发明授权Power-on sequencing apparatus for initializing and testing a system processing unit 失效用于初始化和测试系统处理单元的上电排序装置
公开(公告)号：US5491790A
公开(公告)日：1996-02-13
申请号：US231856
申请日：1994-04-22
IPC分类号： G06F1/00 , G06F9/06 , G06F9/445 , G06F11/22 , G06F11/267
CPC分类号： G06F11/2236 , G06F11/22 , G06F9/4403
摘要： A processing unit couples to a system bus in common with a peer processor, a main memory, in addition to other units, and includes a microprocessor which tightly couples to a local memory also accessible from such bus. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which is coupled to the microprocessor and the system bus. The EEPROM unit stores in first and second separate regions, both of which occupy the same address space normally allocated for storing the microprocessor's boot code, on-board diagnostic (OBD) routines and operating system boot routines, respectively. EEPROM control circuits at power-up, condition the EEPROM unit to address the first region for executing OBD routines to verify that the processing unit is operating properly, including the ability to properly issue commands to units connected to the system bus. Following loading of the peer processor operating system, the EEPROM control circuits, in response to commands from the system bus, enable the microprocessor to address the second region for executing boot routines for loading its operating system.
摘要翻译： 除了其他单元之外，处理单元与对等处理器，主存储器共同地耦合到系统总线，并且包括紧密耦合到也可从这样的总线访问的本地存储器的微处理器。 处理单元还包括可寻址的电可擦除可编程只读存储器（EEPROM）单元，其耦合到微处理器和系统总线。 EEPROM单元存储在第一和第二分离区域中，两者分别占据通常分配用于存储微处理器引导代码，车载诊断（OBD）例程和操作系统引导例程的相同地址空间。 EEPROM控制电路在上电时，使EEPROM单元处理第一个区域以执行OBD例程，以验证处理单元是否正常工作，包括正确向连接到系统总线的单元发出命令的能力。 在加载对等处理器操作系统之后，响应于来自系统总线的命令，EEPROM控制电路使得微处理器能够寻址用于执行用于加载其操作系统的引导例程的第二区域。
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公开(公告)号：US5341501A
公开(公告)日：1994-08-23
申请号：US771582
申请日：1991-10-04
IPC分类号： G06F13/368 , G06F9/46
CPC分类号： G06F13/368
摘要： A high performance microprocessor bus state machine couples to a synchronous local bus in common with another state machine for accessing a local memory according to a preestablished bus protocol. Circuit means cosines the state of a predetermined protocol bus signal indicating the release of the local bus and transitions of the clock signal which are not used for synchronizing the operations of the state machines. The resulting signal applies required address and control signals in advance to the local bus enabling the non-microprocessor state machine to generate the required address strobe to local memory on the next clock which follows the release of the local bus by the microprocessor which eliminates a clock cycle whenever local bus control passes from the microprocessor bus state machine to another state machine.
摘要翻译： 高性能微处理器总线状态机根据预先建立的总线协议与另一状态机共同连接到同步局部总线，用于访问本地存储器。 电路意味着使指示本地总线的释放和不用于同步状态机的操作的时钟信号的转换的预定的协议总线信号的状态。 所产生的信号预先将所需的地址和控制信号施加到本地总线，使得非微处理器状态机能够在微处理器释放本地总线之后的下一个时钟产生所需的地址选通脉冲，从而消除时钟 当本地总线控制从微处理器总线状态机传递到另一状态机时，循环。
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公开(公告)号：US5293384A
公开(公告)日：1994-03-08
申请号：US771581
申请日：1991-10-04
申请人： James W. Keeley , Richard A. Lemay
发明人： James W. Keeley , Richard A. Lemay
CPC分类号： G06F13/4217
摘要： A high performance microprocessor has associated therewith, protocol monitoring apparatus for monitoring all of the commands issued by the microprocessor and detecting when the protocol was not completed properly or completed within certain preestablished periods of time. When the monitor/timing circuits detect a protocol error, the monitoring apparatus operates to generate an output control signal which unwedges the microprocessor enabling it to continue further processing. Additionally, the monitoring apparatus includes a register for storing the address and command that the microprocessor was executing at the time of the protocol error. The same register is also used to capture address and command information for any other type of error.
摘要翻译： 高性能微处理器与其相关联，用于监视由微处理器发出的所有命令的协议监视装置，以及检测协议何时未正确完成或在某些预先建立的时间段内完成。 当监视器/定时电路检测到协议错误时，监视装置操作以产生输出控制信号，该输出控制信号使微处理器能够继续进行进一步的处理。 此外，监视装置包括用于存储微处理器在协议错误时执行的地址和命令的寄存器。 相同的寄存器也用于捕获任何其他类型错误的地址和命令信息。
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公开(公告)号：US4964037A
公开(公告)日：1990-10-16
申请号：US19898
申请日：1987-02-27
IPC分类号： G06F12/06
CPC分类号： G06F12/0623
摘要： A memory address controller addresses two memories and selectively modifies an address before it is applied to the addressing input of one of the two memories. A bit of the address is used to indicate to the controller if the address is to be modified. The same address is applied unchanged to the addressing input of the other of the two memories by the memory address controller. In this manner the addressing range is expanded.
摘要翻译： 存储器地址控制器寻址两个存储器，并且在将地址应用于两个存储器之一的寻址输入之前选择性地修改地址。 地址的一部分用于向控制器指示是否要修改地址。 通过存储器地址控制器将相同的地址不变地应用于两个存储器中的另一个的寻址输入。 以这种方式扩展了寻址范围。
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公开(公告)号：US4467416A
公开(公告)日：1984-08-21
申请号：US302898
申请日：1981-09-16
CPC分类号： G06F9/325 , G06F9/3016
摘要： A logic control system is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system to a CPU without compromising memory bandwidths or CPU execution speeds because of transfer delays or timing variances. Instruction modifications and plural task assignments are accommodated during instruction execution.
摘要翻译： 公开了一种逻辑控制系统，用于将过程信息和CPU（中央处理单元）指令的流程从中央存储器系统适应到CPU，而不会因为传输延迟或定时方差而危及存储器带宽或CPU执行速度。 在指令执行期间容纳指令修改和多任务分配。
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公开(公告)号：US4455606A
公开(公告)日：1984-06-19
申请号：US302902
申请日：1981-09-16
CPC分类号： G06F13/4234 , G06F13/16
摘要： This disclosure relates to a control system for transferring binary words from a memory system. One thirty two bit double word may be loaded into a selected two of four sixteen bit registers. As a first of the two selected registers is read, another thirty two bit word may be loaded into the unselected registers. Alternatively, sixteen bit single words may be loaded into and read from the registers. When a word has procedural information, it is read from the registers onto a CPU control bus via a multiplexer. When a word is an encoded computer instruction to the CPU, it is read from the registers into a logic unit via a multiplexer. A decoded instruction from the logic unit is read onto a CPU control bus.
摘要翻译： 本公开涉及一种用于从存储器系统传送二进制字的控制系统。 一个三十二位双字可能被加载到四个16位寄存器中选定的两个。 由于读取了两个选定的寄存器中的第一个，可以将另外三十二位的位加载到未选择的寄存器中。 或者，可以将16位单个字加载到寄存器中并从寄存器读取。 当一个单词具有程序信息时，它通过多路复用器从寄存器读取到CPU控制总线上。 当一个字为CPU的编码计算机指令时，它通过多路复用器从寄存器读入逻辑单元。 来自逻辑单元的解码指令被读取到CPU控制总线上。
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公开(公告)号：US4254462A
公开(公告)日：1981-03-03
申请号：US911635
申请日：1978-06-01
CPC分类号： G06F13/385
摘要： A hardware/firmware control system is disclosed for accommodating the concurrent bi-directional transfer of information between a communications channel such as a telephone line and a communications processor in a data processing system.
摘要翻译： 公开了一种硬件/固件控制系统，用于在诸如电话线的通信信道和数据处理系统中的通信处理器之间容纳信息的同时双向传送。
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30.发明授权Transfer control technique between two units included in a data processing system 失效包括在数据处理系统中的两个单元之间的传输控制技术
公开(公告)号：US4225921A
公开(公告)日：1980-09-30
申请号：US947990
申请日：1978-10-02
CPC分类号： G06F9/226 , G06F13/4239
摘要： A data processing unit's request to a data processing device for the transfer of control and processing of an operation in response to an instruction from the unit, is stalled by the device, dependent on the type of instruction, for a period of time, also dependent on the type of instruction, until the device is ready to process such operation. A shift register arrangement is used in the device, which, dependent on the indicia stored therein, which indicia are appropriately loaded in such register dependent on the type of instruction, is used to delay a response to the unit by requesting the unit to make another request to the device to process the operation called for by the instruction.
摘要翻译： 数据处理单元响应于来自该单元的指令传送控制和处理操作的数据处理设备的请求被设备停止，取决于指令的类型一段时间，也依赖于 对指令的类型，直到设备准备好处理这样的操作。 在设备中使用移位寄存器装置，其根据存储在其中的标记，根据指令的类型将哪个标记适当地加载在这样的寄存器中，用于通过请求单元进行另一个来延迟对单元的响应 请求设备处理由指令调用的操作。
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