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公开(公告)号:US20180198597A1
公开(公告)日:2018-07-12
申请号:US15863983
申请日:2018-01-08
Applicant: Novatek Microelectronics Corp.
Inventor: Chang-Cheng Huang , Shen-Iuan Liu , Ju-Lin Huang , Tzu-Chien Tzeng , Keko-Chun Liang , Yu-Hsiang Wang , Che-Wei Yeh
CPC classification number: H04L7/0016 , H03L7/0807 , H03L7/087 , H03L7/0891 , H03L7/0898 , H03L7/091 , H03L7/093 , H03L2207/06
Abstract: A clock and data recovery circuit with jitter tolerance enhancement is provided. The CDR circuit includes: a bang-bang phase detector, a digital filter, a digitally controlled oscillator, and an adaptive loop gain control circuit. The CDR circuit detects a loop bandwidth variation and adjusts the loop bandwidth of CDR circuit by adjusting proportional path and integral path gain factors of the digital filter of the CDR circuit. The loop gain controller uses two methods to adjust the loop gain in CDR circuit: bang-bang adjusting method and linear adjusting method.
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公开(公告)号:US20130241631A1
公开(公告)日:2013-09-19
申请号:US13717648
申请日:2012-12-17
Applicant: NOVATEK MICROELECTRONICS CORP.
Inventor: Ju-Lin Huang , Keko-Chun Liang , Chun-Yung Cho , Cheng-Hung Chen
IPC: G05F3/16
Abstract: An output stage circuit includes: a first transistor, including a first terminal coupled to a first node, a second terminal coupled to an output terminal, a third terminal coupled to an input terminal for receiving an input voltage, and a fourth terminal coupled to a first power terminal for receiving a first voltage; a second transistor, including a first terminal coupled to a second node, a second terminal coupled to the output terminal, a third terminal coupled to the input terminal for receiving the input voltage, and a fourth terminal coupled to ground; and a current source, coupled to the output terminal for providing a constant current.
Abstract translation: 输出级电路包括:第一晶体管,包括耦合到第一节点的第一端子,耦合到输出端子的第二端子,耦合到用于接收输入电压的输入端子的第三端子,以及耦合到第一端子的第四端子 用于接收第一电压的第一电源端子; 第二晶体管,包括耦合到第二节点的第一端子,耦合到输出端子的第二端子,耦合到输入端子用于接收输入电压的第三端子和耦合到地的第四端子; 以及耦合到输出端子以提供恒定电流的电流源。
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公开(公告)号:US20230005451A1
公开(公告)日:2023-01-05
申请号:US17945082
申请日:2022-09-14
Applicant: NOVATEK Microelectronics Corp.
Inventor: Che-Wei Yeh , Keko-Chun Liang , Yu-Hsiang Wang , Yong-Ren Fang , Yi-Chuan Liu , Yi-Yang Tsai , Po-Hsiang Fang
IPC: G09G5/12
Abstract: A control system includes a plurality of driving circuits coupled in series, which include a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a first flag signal selector. The first transmitter is coupled to the first receiver, and the first flag signal selector is coupled between the first receiver and the first transmitter. The second driving circuit, coupled to the first driving circuit, includes a second receiver, a second transmitter and a second flag signal selector. The second transmitter is coupled to the second receiver, and the second flag signal selector is coupled between the second receiver and the second transmitter.
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公开(公告)号:US11545081B2
公开(公告)日:2023-01-03
申请号:US17721337
申请日:2022-04-14
Applicant: Novatek Microelectronics Corp.
Inventor: Che-Wei Yeh , Keko-Chun Liang , Yu-Hsiang Wang , Yong-Ren Fang , Yi-Chuan Liu
IPC: G09G3/32
Abstract: A LED driving apparatus with clock embedded cascaded LED drivers is introduced, including: a plurality of LED drivers, wherein the first stage LED driver receives an original data signal and outputs a first data signal, the Nth stage LED driver receives a (N−1)th data signal and outputs a Nth data signal. The Nth stage LED driver includes a clock data recovery circuit generating a recovery clock signal and a recovery data signal according to the (N−1)th data signal; and a first transmitter outputting the Nth data signal according to the recovery clock signal and the recovery data signal.
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公开(公告)号:US20220345123A1
公开(公告)日:2022-10-27
申请号:US17239671
申请日:2021-04-25
Applicant: NOVATEK Microelectronics Corp.
Inventor: Che-Wei Yeh , Keko-Chun Liang , Yu-Hsiang Wang , Yi-Chuan Liu
Abstract: A clock generator includes a pulse generator and a duty cycle correction circuit. The pulse generator is configured to receive an input clock signal and generate a pulse signal according to the input clock signal. The duty cycle correction circuit, coupled to the pulse generator, is configured to adjust a duty cycle of the pulse signal to generate an output clock signal.
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公开(公告)号:US11430382B2
公开(公告)日:2022-08-30
申请号:US17409824
申请日:2021-08-24
Applicant: Novatek Microelectronics Corp.
Inventor: Che-Wei Yeh , Keko-Chun Liang , Yu-Hsiang Wang , Po-Hsiang Fang , Ju-Lin Huang
IPC: G09G3/32
Abstract: A LED driving apparatus with differential signal interfaces is introduced, including: N-stages LED drivers, wherein the first stage LED driver receives a first data packet differential signal and a first clock differential signal and outputs a second data packet differential signal and a second clock differential signal, the Mth stage LED driver receives a Mth data packet differential signal and a Mth clock differential signal and outputs a (M+1)th data packet differential signal and a (M+1)th clock differential signal.
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公开(公告)号:US11170702B2
公开(公告)日:2021-11-09
申请号:US17004025
申请日:2020-08-27
Applicant: Novatek Microelectronics Corp.
Inventor: Che-Wei Yeh , Keko-Chun Liang , Yu-Hsiang Wang , Po-Hsiang Fang , Ju-Lin Huang
IPC: G09G3/32
Abstract: A LED driving apparatus with differential signal interfaces is introduced, including: N-stages LED drivers, wherein the first stage LED driver receives a first data packet differential signal and a first clock differential signal and outputs a second data packet differential signal and a second clock differential signal, the Mth stage LED driver receives a Mth data packet differential signal and a Mth clock differential signal and outputs a (M+1)th data packet differential signal and a (M+1)th clock differential signal.
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公开(公告)号:US20210150976A1
公开(公告)日:2021-05-20
申请号:US16953364
申请日:2020-11-20
Applicant: NOVATEK Microelectronics Corp.
Inventor: Hsu-Chih Wei , Po-Hsiang Fang , Keko-Chun Liang , Che-Wei Yeh , Ju-Lin Huang
IPC: G09G3/32
Abstract: The present disclosure provides a method for a display driver system and a display driver system. The method comprises: the control circuit transmitting a global signal and a first signal for a LED driver circuit in each stage to a first-stage LED driver circuit, wherein the global signal includes an command for indicating an operation mode of the LED driver circuit in each stage; the LED driver circuit in each stage determining the operation mode corresponding to the command according to the global signal, identifying a corresponding first signal of the LED driver circuit in the stage, and operating according to the determined operation mode and the corresponding first signal; and the LED driver circuit in each stage except for last stage transmitting the global signal to the LED driver circuit in its next stage, and in response to a completion of operation according to the determined operation mode and the corresponding first signal, transmitting the first signal for the LED driver circuit in each of sequential stages to the LED driver circuit in its next stage.
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公开(公告)号:US20200350868A1
公开(公告)日:2020-11-05
申请号:US16929124
申请日:2020-07-15
Applicant: Novatek Microelectronics Corp.
Inventor: Chia-Wei Su , Ju-Lin Huang , Keko-Chun Liang
Abstract: An amplifier circuit including an input amplifier, an output amplifier and a diode device is provided. The output amplifier includes a PMOSFET and an NMOSFET. The PMOSFET has a gate electrode serving as a first input end and a drain coupled to an output end. The NMOSFET has a gate electrode serving as a second input end and a drain coupled to the output end. The output amplifier outputs an output voltage at the output end, and is coupled to the input amplifier via at least one of the first and second input ends. The diode device is coupled between the output end and the at least one of the first and second input ends of the output amplifier. When a voltage difference between the output end and the at least one of the first and second input ends of the output amplifier is greater than a barrier voltage of the diode device, the diode device is turned on, and an overshoot of the output voltage is reduced.
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30.
公开(公告)号:US10425043B1
公开(公告)日:2019-09-24
申请号:US15970872
申请日:2018-05-03
Applicant: Novatek Microelectronics Corp.
Inventor: Jhih-Siou Cheng , Keko-Chun Liang
Abstract: An operational amplifier with a constant transconductance bias circuit and a method thereof are introduced. The operational amplifier includes a differential difference amplifier and the constant transconductance bias circuit. The differential difference amplifier has at least one first differential transistor pair and at least one second differential transistor pair. The constant transconductance bias circuit is electrically connected to the differential difference amplifier, and configured to output a first bias voltage to bias the at least one first differential transistor pair and output a second bias voltage to bias the at least one second differential transistor pair. The first bias voltage and the second bias voltage are configured to maintain constant transconductance of the differential difference amplifier.
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