公开(公告)号：US20240428366A1

公开(公告)日：2024-12-26

申请号：US18214447

申请日：2023-06-26

Applicant: NVIDIA Corporation

Inventor： Fnu Vishnuswaroop Ramesh ,  Vivek Belve Kini ,  Jeremy Iverson ,  Nishank Niranjan Chandawala ,  Dimitar Haralampiev Haralanov ,  Mark Hairgrove

IPC: G06T1/60 ,  G06T1/20

Abstract: Apparatuses, systems, and techniques to access one or more non-uniform memory access (NUMA) nodes. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause one or more NUMA nodes or one or more physical addresses allocated to one or more graphics processing units (GPUs) to be accessed based, at least in part, on one or more indications within the API.

公开(公告)号：US20230297696A1

公开(公告)日：2023-09-21

申请号：US18185654

申请日：2023-03-17

Applicant: NVIDIA Corporation

Inventor： Philip Rogers ,  Mark Overby ,  Vyas Venkataraman ,  Naveen Cherukuri ,  James Leroy Deming ,  Gobikrishna Dhanuskodi ,  Dwayne Swoboda ,  Lucien Dunning ,  Aruna Manjunatha ,  Aaron Jiricek ,  Mark Hairgrove ,  Michael Woodmansee

IPC: G06F21/60 ,  G06F9/455 ,  G06F21/57

CPC classification number: G06F21/602 ,  G06F9/45558 ,  G06F21/575 ,  G06F2009/45587

Abstract: In examples, a parallel processing unit (PPU) operates within a trusted execution environment (TEE) implemented using a central processing unit (CPU). A virtual machine (VM) executing within the TEE is provided access to the PPU by a hypervisor. However, data of an application executed by the VM is inaccessible to the hypervisor and other untrusted entities outside of the TEE. To protect the data in transit, the VM and the PPU may encrypt or decrypt the data for secure communication between the devices. To protect the data within the PPU, a protected memory region may be created in PPU memory where compute engines of the PPU are prevented from writing outside of the protected memory region. A write protect memory region is generated where access to the PPU memory is blocked from other computing devices and/or device instances.

公开(公告)号：US11487673B2

公开(公告)日：2022-11-01

申请号：US14055345

申请日：2013-10-16

Applicant: NVIDIA Corporation

Inventor： Jerome F. Duluk, Jr. ,  Cameron Buschardt ,  Sherry Cheung ,  James Leroy Deming ,  Samuel H. Duncan ,  Lucien Dunning ,  Robert George ,  Arvind Gopalakrishnan ,  Mark Hairgrove ,  Chenghuan Jia ,  John Mashey

IPC: G06F13/12 ,  G06F13/38 ,  G06F12/1009 ,  G06F12/109 ,  G06F12/1072 ,  G06F12/08 ,  G06F11/07 ,  G06F12/12 ,  G06F12/10

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

公开(公告)号：US10546361B2

公开(公告)日：2020-01-28

申请号：US15709397

申请日：2017-09-19

Applicant: NVIDIA Corporation

Inventor： Stephen Jones ,  Vivek Kini ,  Piotr Jaroszynski ,  Mark Hairgrove ,  David Fontaine ,  Cameron Buschardt ,  Lucien Dunning ,  John Hubbard

IPC: G06F13/14 ,  G06T1/20 ,  G06F9/50 ,  G06F12/109 ,  G06T1/60

Abstract: The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one exemplary implementation, an address allocation process comprises: establishing space for managed pointers across a plurality of memories, including allocating one of the managed pointers with a first portion of memory associated with a first one of a plurality of processors; and performing a process of automatically managing accesses to the managed pointers across the plurality of processors and corresponding memories. The automated management can include ensuring consistent information associated with the managed pointers is copied from the first portion of memory to a second portion of memory associated with a second one of the plurality of processors based upon initiation of an accesses to the managed pointers from the second one of the plurality of processors.

公开(公告)号：US20190147561A1

公开(公告)日：2019-05-16

申请号：US16237010

申请日：2018-12-31

Applicant: Nvidia Corporation

Inventor： Stephen Jones ,  Vivek Kini ,  Piotr Jaroszynski ,  Mark Hairgrove ,  David Fontaine ,  Cameron Buschardt ,  Lucien Dunning ,  John Hubbard

IPC: G06T1/20 ,  G06F9/50 ,  G06F12/109 ,  G06T1/60

Abstract: The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one exemplary implementation, an address allocation process comprises: establishing space for managed pointers across a plurality of memories, including allocating one of the managed pointers with a first portion of memory associated with a first one of a plurality of processors; and performing a process of automatically managing accesses to the managed pointers across the plurality of processors and corresponding memories. The automated management can include ensuring consistent information associated with the managed pointers is copied from the first portion of memory to a second portion of memory associated with a second one of the plurality of processors based upon initiation of an accesses to the managed pointers from the second one of the plurality of processors.

公开(公告)号：US10133677B2

公开(公告)日：2018-11-20

申请号：US14133489

申请日：2013-12-18

Applicant: NVIDIA CORPORATION

Inventor： Jerome F. Duluk, Jr. ,  Cameron Buschardt ,  James Leroy Deming ,  Lucien Dunning ,  Brian Fahs ,  Mark Hairgrove ,  John Mashey

IPC: G06F12/12 ,  G06F12/122 ,  G06F12/08 ,  G06F12/1009

Abstract: Techniques are disclosed for transitioning a memory page between memories in a virtual memory subsystem. A unified virtual memory (UVM) driver detects a page fault in response to a memory access request associated with a first memory page, where a local page table does not include an entry corresponding to a virtual memory address included in the memory access request. The UVM driver, in response to the page fault, executes a page fault sequence. The page fault sequence includes modifying the ownership state associated with the first memory page to be central-processing-unit-shared. The page fault sequence further includes scheduling the first memory page for migration from a system memory associated with a central processing unit (CPU) to a local memory associated with a parallel processing unit (PPU). One advantage of the disclosed approach is that the PPU accesses memory pages with greater efficiency.

公开(公告)号：US10037228B2

公开(公告)日：2018-07-31

申请号：US13660763

申请日：2012-10-25

Applicant: NVIDIA Corporation

Inventor： Nick Barrow-Williams ,  Brian Fahs ,  Jerome F. Duluk, Jr. ,  James Leroy Deming ,  Timothy John Purcell ,  Lucien Dunning ,  Mark Hairgrove

IPC: G06F12/00 ,  G06F9/50 ,  G06F12/1045 ,  G06F12/109

CPC classification number: G06F9/5027 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109

Abstract: A technique for simultaneously executing multiple tasks, each having an independent virtual address space, involves assigning an address space identifier (ASID) to each task and constructing each virtual memory access request to include both a virtual address and the ASID. During virtual to physical address translation, the ASID selects a corresponding page table, which includes virtual to physical address mappings for the ASID and associated task. Entries for a translation look-aside buffer (TLB) include both the virtual address and ASID to complete each mapping to a physical address. Deep scheduling of tasks sharing a virtual address space may be implemented to improve cache affinity for both TLB and data caches.

公开(公告)号：US09767036B2

公开(公告)日：2017-09-19

申请号：US14055318

申请日：2013-10-16

Applicant: NVIDIA Corporation

Inventor： Jerome F. Duluk, Jr. ,  Cameron Buschardt ,  Sherry Cheung ,  James Leroy Deming ,  Samuel H. Duncan ,  Lucien Dunning ,  Robert George ,  Arvind Gopalakrishnan ,  Mark Hairgrove ,  Chenghuan Jia ,  John Mashey

IPC: G06F12/10 ,  G06F12/1009 ,  G06F12/109 ,  G06F12/1072 ,  G06F11/07 ,  G06F12/12 ,  G06F12/08

CPC classification number: G06F12/1009 ,  G06F11/073 ,  G06F11/0793 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1072 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/1016

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

公开(公告)号：US09519568B2

公开(公告)日：2016-12-13

申请号：US13732282

申请日：2012-12-31

Applicant: NVIDIA Corporation

Inventor： Mayank Kaushik ,  Alban Douillet ,  Geoffrey Gerfin ,  Vyas Venkataraman ,  Mark Hairgrove ,  Riley Andrews

IPC: G06F9/44 ,  G06F11/36

CPC classification number: G06F11/3636 ,  G06F11/3624

Abstract: A system and method for debugging an executing program. The method includes executing a general-purpose computing on graphics processing units (GPGPU) program. The GPGPU program comprises a first portion operable to execute on a central processing unit (CPU) and a second portion operable to execute on a graphics processing unit (GPU). The method further includes attaching a debugging program to the first portion of the GPGPU program and modifying the first portion of the GPGPU program. The attaching of the debugging program to the first portion of the GPGPU program pauses execution of the first portion of the GPGPU program. The method further includes resuming execution of the first portion of the GPGPU program and accessing a first state information corresponding to the first portion of the GPGPU program. Execution of the first portion of the GPGPU program may then be paused. The first state information may then be used to access a second state information corresponding to the second portion of the GPGPU program.

Abstract translation: 一种用于调试执行程序的系统和方法。 该方法包括对图形处理单元（GPGPU）程序执行通用计算。 GPGPU程序包括可操作以在中央处理单元（CPU）上执行的第一部分和可操作以在图形处理单元（GPU）上执行的第二部分。 该方法还包括将调试程序附加到GPGPU程序的第一部分并修改GPGPU程序的第一部分。 将调试程序附加到GPGPU程序的第一部分暂停执行GPGPU程序的第一部分。 该方法还包括恢复GPGPU程序的第一部分的执行和访问对应于GPGPU程序的第一部分的第一状态信息。 然后可以暂停执行GPGPU程序的第一部分。 然后可以使用第一状态信息来访问对应于GPGPU程序的第二部分的第二状态信息。

公开(公告)号：US20140189647A1

公开(公告)日：2014-07-03

申请号：US13732282

申请日：2012-12-31

Applicant: NVIDIA CORPORATION

Inventor： Mayank Kaushik ,  Alban Douillet ,  Geoffrey Gerfin ,  Vyas Venkataraman ,  Mark Hairgrove ,  Riley Andrews

IPC: G06F11/36

CPC classification number: G06F11/3636 ,  G06F11/3624

Abstract: A system and method for debugging an executing program. The method includes executing a general-purpose computing on graphics processing units (GPGPU) program. The GPGPU program comprises a first portion operable to execute on a central processing unit (CPU) and a second portion operable to execute on a graphics processing unit (GPU). The method further includes attaching a debugging program to the first portion of the GPGPU program and modifying the first portion of the GPGPU program. The attaching of the debugging program to the first portion of the GPGPU program pauses execution of the first portion of the GPGPU program. The method further includes resuming execution of the first portion of the GPGPU program and accessing a first state information corresponding to the first portion of the GPGPU program. Execution of the first portion of the GPGPU program may then be paused. The first state information may then be used to access a second state information corresponding to the second portion of the GPGPU program.

Abstract translation: 一种用于调试执行程序的系统和方法。 该方法包括对图形处理单元（GPGPU）程序执行通用计算。 GPGPU程序包括可操作以在中央处理单元（CPU）上执行的第一部分和可操作以在图形处理单元（GPU）上执行的第二部分。 该方法还包括将调试程序附加到GPGPU程序的第一部分并修改GPGPU程序的第一部分。 将调试程序附加到GPGPU程序的第一部分暂停执行GPGPU程序的第一部分。 该方法还包括恢复GPGPU程序的第一部分的执行和访问对应于GPGPU程序的第一部分的第一状态信息。 然后可以暂停执行GPGPU程序的第一部分。 然后可以使用第一状态信息来访问对应于GPGPU程序的第二部分的第二状态信息。