公开(公告)号：US06472714B1

公开(公告)日：2002-10-29

申请号：US09649107

申请日：2000-08-28

申请人： Sadaaki Masuoka ,  Kiyotaka Imai

发明人： Sadaaki Masuoka ,  Kiyotaka Imai

IPC分类号： H01L2976

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903

摘要： A core section complementary transistor and a memory cell section complementary transistor are formed on a semiconductor substrate of a first conductivity type. The core section complementary transistor has a first well of a second conductivity type provided in the semiconductor substrate, a first core section MOS transistor provided on the first well of the second conductivity type, a second core section MOS transistor provided on the semiconductor substrate a device separation film which separates the first core section MOS transistor and the second core section MOS transistor from each other, and a well of the first conductivity type provided under a part of the device separation film which is closer to the second core section MOS transistor. The first core section MOS transistor has source-drain regions of the first conductivity type. The second core section MOS transistor has source-drain regions of the second conductivity type. The well of the first conductivity type has an impurity concentration higher than that of the semiconductor substrate.

摘要翻译： 核心部分互补晶体管和存储单元部分互补晶体管形成在第一导电类型的半导体衬底上。 芯部互补晶体管具有设置在半导体衬底中的第二导电类型的第一阱，设置在第二导电类型的第一阱上的第一芯部MOS晶体管，设置在半导体衬底上的第二芯部MOS晶体管，器件 将第一芯部MOS晶体管和第二芯部MOS晶体管彼此分离的分离膜以及设置在更靠近第二芯部MOS晶体管的器件分离膜的一部分下方的第一导电类型的阱。 第一芯部MOS晶体管具有第一导电类型的源极 - 漏极区域。 第二核心部分MOS晶体管具有第二导电类型的源极 - 漏极区域。 第一导电类型的阱的杂质浓度高于半导体衬底的杂质浓度。

公开(公告)号：US06368754B1

公开(公告)日：2002-04-09

申请号：US09442251

申请日：1999-11-15

申请人： Kiyotaka Imai

发明人： Kiyotaka Imai

IPC分类号： G03F900

CPC分类号： G03F1/00

摘要： There is provided a reticle used for fabrication of a semiconductor device, including (a) a first area in which a first mask having a first pattern is formed for forming a first contact hole having a first size, and (b) a second area in which a second mask having a second pattern is formed for forming a second contact hole having a second size different from the first size. The reticle makes it possible to transfer a contact pattern to a resist film in exposure conditions suitable for a size of a contact hole. Thus, a contact hole is transferred to a resist film in a designed dimension regardless of a size thereof.

摘要翻译： 提供了用于制造半导体器件的掩模版，其包括（a）第一区域，其中形成具有第一图案的第一掩模以形成具有第一尺寸的第一接触孔，以及（b）第二区域 形成具有第二图案的第二掩模，用于形成具有与第一尺寸不同的第二尺寸的第二接触孔。 掩模版使得可以在适合于接触孔尺寸的曝光条件下将接触图案转印到抗蚀剂膜上。 因此，无论其尺寸如何，接触孔都以设计尺寸转移到抗蚀剂膜。

公开(公告)号：US06297529B1

公开(公告)日：2001-10-02

申请号：US09286334

申请日：1999-04-05

申请人： Kiyotaka Imai

发明人： Kiyotaka Imai

IPC分类号： H01L2182

CPC分类号： H01L21/28052 ,  H01L29/4933 ,  H01L29/665

摘要： A semiconductor device is provided which is capable of suppressing an increase in the layer resistance of the gate electrode and preventing an increase of the contact resistance of the gate electrode with the silicide layer. The above properties of the semiconductor device are provided by forming the gate electrode comprising multiple layers, and the lowermost layer of the gate electrode is doped with an impurity, and other upper layers are formed undoped.

摘要翻译： 提供一种半导体器件，其能够抑制栅电极的层电阻的增加，并防止栅电极与硅化物层的接触电阻增加。半导体器件的上述性质通过形成栅极 电极包括多层，并且栅电极的最下层掺杂有杂质，其它上层形成为未掺杂的。

公开(公告)号：US06222234B1

公开(公告)日：2001-04-24

申请号：US09288314

申请日：1999-04-08

申请人： Kiyotaka Imai

发明人： Kiyotaka Imai

IPC分类号： H01L2900

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： The invention provides a semiconductor device that has a fully depleted MOSFET and a partially depleted MOSFET having excellent characteristics on the same substrate without effecting control by means of the impurity concentration of the channel region. A semiconductor device is provided with a fully-depleted SOI MOSFET and a partially-depleted SOI MOSFET on the same SOI substrate through isolation by an element isolation film. The SOI substrate includes a buried oxide film and SOI layer provided in succession on a silicon substrate.

摘要翻译： 本发明提供一种半导体器件，其具有完全耗尽的MOSFET和在相同衬底上具有优异特性的部分耗尽的MOSFET，而不通过沟道区的杂质浓度进行控制。 半导体器件通过元件隔离膜隔离在同一SOI衬底上提供完全耗尽的SOI MOSFET和部分耗尽的SOI MOSFET。 SOI衬底包括在硅衬底上连续提供的掩埋氧化物膜和SOI层。

公开(公告)号：US6150202A

公开(公告)日：2000-11-21

申请号：US90937

申请日：1998-06-05

申请人： Kiyotaka Imai ,  Hideaki Onishi

发明人： Kiyotaka Imai ,  Hideaki Onishi

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/786

CPC分类号： H01L21/76264 ,  H01L21/84

摘要： Disclosed is a method for fabricating semiconductor device, which has the steps of: forming a device separation region to section a first device forming region and a second device forming region on a substrate with a SOI structure; forming gate oxide film on the first and second device forming regions; introducing first conductivity type impurity and second conductivity type impurity into the first and second device forming regions to form a channel region of a first channel type transistor by the first conductivity type impurity and to form a source-drain region of the first channel type transistor by the second conductivity type impurity on at least the first device forming region; and introducing the first conductivity type impurity and the second conductivity type impurity selectively into the second device forming region to form a channel region and a source-drain region of a second channel type transistor on the second device forming region.

摘要翻译： 本发明公开了一种制造半导体器件的方法，其特征在于包括以下步骤：在具有SOI结构的衬底上形成第一器件形成区域和第二器件形成区域的器件分离区域; 在第一和第二器件形成区上形成栅氧化膜; 将第一导电型杂质和第二导电型杂质引入到第一和第二器件形成区域中，以通过第一导电类型杂质形成第一沟道型晶体管的沟道区，并通过第一导电型杂质形成第一沟道型晶体管的源极 - 漏极区 至少在第一器件形成区域上的第二导电型杂质; 并且将第一导电类型杂质和第二导电类型杂质选择性地引入到第二器件形成区域中，以在第二器件形成区域上形成沟道区域和第二沟道型晶体管的源极 - 漏极区域。

公开(公告)号：US5569611A

公开(公告)日：1996-10-29

申请号：US330361

申请日：1994-10-12

申请人： Kiyotaka Imai

发明人： Kiyotaka Imai

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L29/66287 ,  H01L29/0821 ,  H01L29/732 ,  H01L29/0826 ,  Y10S148/01 ,  Y10S148/011 ,  Y10S148/024 ,  Y10S148/035 ,  Y10S148/036 ,  Y10S438/921 ,  Y10S438/969

摘要： In a method of manufacturing a bipolar transistor, an oxide film pattern is formed on an epitaxial collector layer of a first conductive type which is formed on a buried layer of the first conductive type. A selectively-ion-implanted-collector (SIC) region is then formed in the collector layer, and after that, a base layer is grown on the SIC region with an inversely graded impurity distribution profile.

摘要翻译： 在制造双极晶体管的方法中，在形成在第一导电类型的掩埋层上的第一导电类型的外延集电极层上形成氧化膜图案。 然后在集电极层中形成选择性离子注入集电极（SIC）区域，然后在SIC区域上生长具有反向分级杂质分布分布的基极层。

公开(公告)号：US5508537A

公开(公告)日：1996-04-16

申请号：US267386

申请日：1994-06-29

申请人： Kiyotaka Imai

发明人： Kiyotaka Imai

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/732 ,  H01L29/737 ,  H01L31/0328 ,  H01L27/082 ,  H01L31/072

CPC分类号： H01L29/7378

摘要： A collector layer of a first electrically conductive type is surrounded by an oxide film for separating elements. A base layer comprising an epitaxial layer of a second electrically conductive type is formed on the collector layer. A polysilicon film of the second electrically conductive type is formed at a first area of a surface of the base layer. An emitter layer of the first electrically conductive type is formed at a second area of a surface of the base layer. A base polysilicon electrode comprising of the second electrically conductive type is formed on the polysilicon film and on the oxide film for separating elements. A sidewall comprising an insulating film is formed over a lateral wall of the base polysilicon electrode and a lateral wall of the polysilicon film. An emitter polysilicon electrode of the first electrically conductive type is formed over the emitter layer and the side wall.

摘要翻译： 第一导电类型的集电极层被用于分离元件的氧化膜包围。 在收集层上形成包含第二导电类型的外延层的基底层。 第二导电类型的多晶硅膜形成在基层的表面的第一区域。 第一导电类型的发射极层形成在基层的表面的第二区域。 包含第二导电类型的基底多晶硅电极形成在多晶硅膜上和用于分离元件的氧化物膜上。 在基底多晶硅电极的侧壁和多晶硅膜的侧壁上形成包括绝缘膜的侧壁。 在发射极层和侧壁上形成第一导电类型的发射极多晶硅电极。

公开(公告)号：US08389350B2

公开(公告)日：2013-03-05

申请号：US13178248

申请日：2011-07-07

申请人： Akihito Sakakidani ,  Kiyotaka Imai

发明人： Akihito Sakakidani ,  Kiyotaka Imai

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28202 ,  H01L21/28229 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/6659

摘要： A method of manufacturing N-type MOSFET includes: implanting a p-type dopant into in a surface layer of a semiconductor substrate to form a channel region; forming a gate insulating film including High-k material and a gate electrode on said channel region; implanting a p-type dopant into both ends of said channel region in an inner portion of said semiconductor substrate to form halo regions; implanting a p-type dopant into both ends of said channel region in a surface layer of said semiconductor substrate to form extension regions. One of said step of forming said channel region and said step of forming halo regions includes: implanting C into one of said channel region and said halo regions. An inclusion amount of said High-k material is an amount that increase of a threshold voltage caused by said High-k material being included in said gate insulating film compensates for decrease of said threshold voltage caused by said C being implanted.

摘要翻译： 一种制造N型MOSFET的方法包括：将p型掺杂剂注入到半导体衬底的表面层中以形成沟道区; 在所述沟道区上形成包括High-k材料和栅电极的栅极绝缘膜; 在所述半导体衬底的内部部分中将p型掺杂剂注入所述沟道区的两端以形成晕圈; 在所述半导体衬底的表面层中将p型掺杂剂注入所述沟道区的两端以形成扩展区。 形成所述通道区域和所述形成晕圈区的步骤的所述步骤之一包括：将C注入所述通道区域和所述晕区域之一。 所述High-k材料的包含量是由包括在所述栅极绝缘膜中的所述High-k材料引起的阈值电压的增加补偿由所述C植入引起的所述阈值电压的降低。

公开(公告)号：US20080093699A1

公开(公告)日：2008-04-24

申请号：US11874221

申请日：2007-10-18

申请人： Tomohisa ABE ,  Gen Tsutsui ,  Tadashi Fukase ,  Yasushi Nakahara ,  Kiyotaka Imai

发明人： Tomohisa ABE ,  Gen Tsutsui ,  Tadashi Fukase ,  Yasushi Nakahara ,  Kiyotaka Imai

IPC分类号： H01L29/00

CPC分类号： H01L21/2652 ,  H01L21/82385 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/105

摘要： The semiconductor device includes a plurality of transistors at least having different channel widths from each other. Threshold voltages of those transistors are set to be substantially equal to each other, by using both of substantially the same channel dose for each of those transistors, and work function control using a predetermined metal to be deposited on a gate insulating of those transistors and/or a gate electrode material of each of those transistors (that is, work function control based on a gate structure (gate insulating film and/or gate electrode) with respect to a channel region of each of those transistors).

摘要翻译： 半导体器件包括至少具有彼此不同沟道宽度的多个晶体管。 这些晶体管的阈值电压通过使用这些晶体管中的每一个的基本上相同的通道剂量和使用要沉积在那些晶体管的栅极绝缘上的预定金属的功函数控制来设置为彼此基本相等，和/ 或这些晶体管中的每一个的栅极电极材料（即，相对于这些晶体管的沟道区域，基于栅极结构（栅极绝缘膜和/或栅电极）的功函数控制）。

公开(公告)号：US06342413B1

公开(公告)日：2002-01-29

申请号：US09693909

申请日：2000-10-23

申请人： Sadaaki Masuoka ,  Kiyotaka Imai

发明人： Sadaaki Masuoka ,  Kiyotaka Imai

IPC分类号： H01L21336

CPC分类号： H01L21/26513 ,  H01L21/2658 ,  H01L21/823412

摘要： In a method of manufacturing a semiconductor device having first through third MOS transistors, using a first mask (311), wells (313, 314) and first threshold adjustment regions (315, 316) are formed at transistor areas (306n, 308n) for the second and the third MOS transistors in a semiconductor substrate (301). Next, using a second mask (319), second threshold adjustment regions (320, 321) are formed at transistor areas (304n and 308n) for the first and the third MOS transistors. In the transistor area for the third MOS transistor, both of the first threshold adjustment region and the second threshold adjustment region form a third adjustment region. Thus, using the two masks, three thresholds of the MOS transistors are obtained.