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51 条记录 (耗时 0.03 秒)

    Methods Of Forming Capacitors
    21.
    发明申请
    Methods Of Forming Capacitors 有权
    形成电容器的方法

    公开(公告)号：US20130164902A1

    公开(公告)日：2013-06-27

    申请号：US13332816

    申请日：2011-12-21

    申请人： Joseph Neil Greeley ,  Prashant Raghu ,  Niraj B. Rana

    发明人： Joseph Neil Greeley ,  Prashant Raghu ,  Niraj B. Rana

    IPC分类号： H01L21/02

    CPC分类号： H01L28/92 ,  H01L21/32133 ,  H01L27/108 ,  H01L27/10852 ,  H01L27/10861 ,  H01L28/90

    摘要： A method of forming capacitors includes forming support material over a substrate. A first capacitor electrode is formed within individual openings in the support material. A first etching is conducted only partially into the support material using a liquid etching fluid to expose an elevationally outer portion of sidewalls of individual of the first capacitor electrodes. A second etching is conducted into the support material using a dry etching fluid to expose an elevationally inner portion of the sidewalls of the individual first capacitor electrodes. A capacitor dielectric is formed over the outer and inner portions of the sidewalls of the first capacitor electrodes. A second capacitor electrode is formed over the capacitor dielectric.

    摘要翻译： 形成电容器的方法包括在衬底上形成支撑材料。 第一电容器电极形成在支撑材料中的各个开口内。 使用液体蚀刻流体仅部分地将第一蚀刻部分地进入支撑材料，以暴露第一电容器电极的各个侧壁的正面外侧部分。 使用干蚀刻流体将第二蚀刻进入支撑材料，以暴露各个第一电容器电极的侧壁的正面内部。 在第一电容器电极的侧壁的外部和内部上形成电容器电介质。 在电容器电介质上形成第二电容电极。

    Transistor gate forming methods and transistor structures
    23.
    发明授权
    Transistor gate forming methods and transistor structures 有权
    晶体管栅极形成方法和晶体管结构

    公开(公告)号：US07867845B2

    公开(公告)日：2011-01-11

    申请号：US11219077

    申请日：2005-09-01

    申请人： Sanh D. Tang ,  Gordon A. Haller ,  Prashant Raghu ,  Ravi Iyer

    发明人： Sanh D. Tang ,  Gordon A. Haller ,  Prashant Raghu ,  Ravi Iyer

    IPC分类号： H01L29/76

    CPC分类号： H01L29/78696 ,  H01L29/42392 ,  H01L29/66787

    摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.

    摘要翻译： 晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。 填充层相对于金属层基本上可选择性地蚀刻。 晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。 如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。 本发明至少应用于三维晶体管结构。

    Methods of etching nickel silicide and cobalt silicide and methods of forming conductive lines
    24.
    发明授权
    Methods of etching nickel silicide and cobalt silicide and methods of forming conductive lines 有权
    蚀刻硅化镍和硅化钴的方法和形成导电线的方法

    公开(公告)号：US07371333B2

    公开(公告)日：2008-05-13

    申请号：US11146648

    申请日：2005-06-07

    申请人： Prashant Raghu

    发明人： Prashant Raghu

    IPC分类号： B44C1/22

    CPC分类号： H01L21/32134 ,  H01L29/66621 ,  H01L29/7834

    摘要： The invention includes methods of etching nickel silicide and cobalt silicide, and methods of forming conductive lines. In one implementation, a substrate comprising nickel silicide is exposed to a fluid comprising H3PO4 and H2O at a temperature of at least 50° C. and at a pressure from 350 Torr to 1100 Torr effective to etch nickel silicide from the substrate. In one implementation, at least one of nickel silicide or cobalt silicide is exposed to a fluid comprising H2SO4, H2O2, H2O, and HF at a temperature of at least 50° C. and at a pressure from 350 Torr to 1100 Torr effective to etch the at least one of nickel silicide or cobalt silicide from the substrate.

    摘要翻译： 本发明包括蚀刻硅化镍和硅化钴的方法，以及形成导电线的方法。 在一个实施方案中，将包含硅化镍的衬底暴露于包含H 3 PO 3 H 2 O 2和H 2 O 2的流体至少 50°C和350 Torr至1100 Torr的压力有效地从衬底上蚀刻硅化镍。 在一个实施方案中，将硅化镍或硅化钴中的至少一种暴露于包含H 2 SO 4 H 2 O 3，H 2 O > 2 H 2 O和HF在至少50℃的温度和350托至1100托的压力下有效地蚀刻至少一种硅化镍 或硅化钴。

    Methods of forming semiconductor constructions
    26.
    发明授权
    Methods of forming semiconductor constructions 有权
    形成半导体结构的方法

    公开(公告)号：US08613864B2

    公开(公告)日：2013-12-24

    申请号：US13593373

    申请日：2012-08-23

    申请人： Prashant Raghu

    发明人： Prashant Raghu

    IPC分类号： C25F3/00

    CPC分类号： H01L21/30604 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91

    摘要： The invention includes methods in which silicon is removed from titanium-containing container structures with an etching composition having a phosphorus-and-oxygen-containing compound therein. The etching composition can, for example, include one or both of ammonium hydroxide and tetra-methyl ammonium hydroxide. The invention also includes methods in which titanium-containing whiskers are removed from between titanium-containing capacitor electrodes. Such removal can be, for example, accomplished with an etch utilizing one or more of hydrofluoric acid, ammonium fluoride, nitric acid and hydrogen peroxide.

    摘要翻译： 本发明包括使用其中含有含磷和氧的化合物的蚀刻组合物从含钛容器结构中除去硅的方法。 蚀刻组合物可以例如包括氢氧化铵和四甲基氢氧化铵中的一种或两种。 本发明还包括从含钛电容器电极之间除去含钛晶须的方法。 这种去除可以例如通过使用氢氟酸，氟化铵，硝酸和过氧化氢中的一种或多种的蚀刻来实现。

    Transistor gate forming methods and transistor structures
    27.
    发明授权
    Transistor gate forming methods and transistor structures 有权
    晶体管栅极形成方法和晶体管结构

    公开(公告)号：US08349687B2

    公开(公告)日：2013-01-08

    申请号：US12977969

    申请日：2010-12-23

    申请人： Sanh D. Tang ,  Gordon A. Haller ,  Prashant Raghu ,  Ravi Iyer

    发明人： Sanh D. Tang ,  Gordon A. Haller ,  Prashant Raghu ,  Ravi Iyer

    IPC分类号： H01L29/76

    CPC分类号： H01L29/78696 ,  H01L29/42392 ,  H01L29/66787

    摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.

    摘要翻译： 晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。 填充层相对于金属层基本上可选择性地蚀刻。 晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。 如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。 本发明至少应用于三维晶体管结构。

    METHODS OF SELECTIVELY FORMING METAL-DOPED CHALCOGENIDE MATERIALS, METHODS OF SELECTIVELY DOPING CHALCOGENIDE MATERIALS, AND METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES INCLUDING SAME
    29.
    发明申请
    METHODS OF SELECTIVELY FORMING METAL-DOPED CHALCOGENIDE MATERIALS, METHODS OF SELECTIVELY DOPING CHALCOGENIDE MATERIALS, AND METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES INCLUDING SAME 有权
    选择性形成金属聚合材料的方法，选择性聚合材料的方法，以及形成包括其中的半导体器件结构的方法

    公开(公告)号：US20120276725A1

    公开(公告)日：2012-11-01

    申请号：US13094024

    申请日：2011-04-26

    申请人： Jerome A. Imonigie ,  Prashant Raghu ,  Theodore M. Taylor ,  Scott E. Sills

    发明人： Jerome A. Imonigie ,  Prashant Raghu ,  Theodore M. Taylor ,  Scott E. Sills

    IPC分类号： H01L21/228 ,  H01B1/02

    CPC分类号： H01L45/1658 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1641

    摘要： Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating transition metal of the transition solution into the chalcogenide material without substantially incorporating the transition metal into an adjacent material. The chalcogenide material is not silver selenide. Another method comprises forming a chalcogenide material adjacent to and in contact with an insulative material, exposing the chalcogenide material and the insulative material to a transition metal solution, and diffusing transition metal of the transition metal solution into the chalcogenide material while substantially no transition metal diffuses into the insulative material. A method of doping a chalcogenide material of a memory cell with at least one transition metal without using an etch or chemical mechanical planarization process to remove the transition metal from an insulative material of the memory cell is also disclosed, wherein the chalcogenide material is not silver selenide.

    摘要翻译： 选择性地形成金属掺杂的硫族化物材料的方法包括将硫族化物材料暴露于过渡金属溶液，并将过渡溶液的过渡金属掺入硫族化物材料中，而基本上不将过渡金属掺入相邻的材料中。 硫族化物材料不是硒化银。 另一种方法包括形成与绝缘材料相邻并与其接触的硫族化物材料，将硫属化物材料和绝缘材料暴露于过渡金属溶液，并将过渡金属溶液的过渡金属扩散到硫属化物材料中，同时基本上没有过渡金属扩散 进入绝缘材料。 还公开了一种使用至少一种过渡金属掺杂存储单元的硫族化物材料而不使用蚀刻或化学机械平坦化工艺以从存储器单元的绝缘材料除去过渡金属的方法，其中硫族化物材料不是银 硒化物

    Methods of Forming Semiconductor Constructions
    30.
    发明申请
    Methods of Forming Semiconductor Constructions 失效
    形成半导体结构的方法

    公开(公告)号：US20100190344A1

    公开(公告)日：2010-07-29

    申请号：US12750457

    申请日：2010-03-30

    申请人： Prashant Raghu

    发明人： Prashant Raghu

    IPC分类号： H01L21/306

    CPC分类号： H01L21/30604 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91

    摘要： The invention includes methods in which silicon is removed from titanium-containing container structures with an etching composition having a phosphorus-and-oxygen-containing compound therein. The etching composition can, for example, include one or both of ammonium hydroxide and tetra-methyl ammonium hydroxide. The invention also includes methods in which titanium-containing whiskers are removed from between titanium-containing capacitor electrodes. Such removal can be, for example, accomplished with an etch utilizing one or more of hydrofluoric acid, ammonium fluoride, nitric acid and hydrogen peroxide.

    摘要翻译： 本发明包括使用其中含有含磷和氧的化合物的蚀刻组合物从含钛容器结构中除去硅的方法。 蚀刻组合物可以例如包括氢氧化铵和四甲基氢氧化铵中的一种或两种。 本发明还包括从含钛电容器电极之间除去含钛晶须的方法。 这种去除可以例如通过使用氢氟酸，氟化铵，硝酸和过氧化氢中的一种或多种的蚀刻来实现。