利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

105 条记录 (耗时 0.057 秒)

    Method of implanting copper barrier material to improve electrical performance
    22.
    发明授权
    Method of implanting copper barrier material to improve electrical performance 失效
    注入铜阻挡材料以改善电气性能的方法

    公开(公告)号：US06835655B1

    公开(公告)日：2004-12-28

    申请号：US09994397

    申请日：2001-11-26

    申请人： Paul R. Besser ,  Matthew S. Buynoski ,  Sergey D. Lopatin

    发明人： Paul R. Besser ,  Matthew S. Buynoski ,  Sergey D. Lopatin

    IPC分类号： H01L2144

    CPC分类号： H01L23/53238 ,  H01L21/76843 ,  H01L21/76859 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of implanting copper barrier material to improve electrical performance in an integrated circuit fabrication process can include providing a copper layer over an integrated circuit substrate, providing a barrier material at a bottom and sides of a via positioned over the copper layer to form a barrier material layer separating the via from the copper layer, implanting a metal species into the barrier material layer, and providing a conductive layer over the via such that the via electrically connects the conductive layer to the copper layer. The implanted metal species can make the barrier material layer more resistant to copper diffusion from the copper layer.

    摘要翻译： 在集成电路制造工艺中注入铜阻挡材料以提高电性能的方法可以包括在集成电路基板上提供铜层，在位于铜层上方的通孔的底部和侧面提供阻挡材料以形成屏障 将所述通孔与所述铜层分离的材料层，将金属物质注入到所述阻挡材料层中，以及在所述通孔上方提供导电层，使得所述通孔将所述导电层电连接到所述铜层。 注入的金属物质可以使阻挡材料层更能抵抗铜层从铜层扩散。

    Method of inserting alloy elements to reduce copper diffusion and bulk diffusion
    23.
    发明授权
    Method of inserting alloy elements to reduce copper diffusion and bulk diffusion 失效
    插入合金元素以减少铜扩散和体扩散的方法

    公开(公告)号：US06703308B1

    公开(公告)日：2004-03-09

    申请号：US09994400

    申请日：2001-11-26

    申请人： Paul R. Besser ,  Matthew S. Buynoski ,  Sergey D. Lopatin ,  Alline F. Myers ,  Phin-Chin Connie Wang

    发明人： Paul R. Besser ,  Matthew S. Buynoski ,  Sergey D. Lopatin ,  Alline F. Myers ,  Phin-Chin Connie Wang

    IPC分类号： H01L2144

    CPC分类号： H01L21/76843 ,  H01L21/76849 ,  H01L21/76859 ,  H01L21/76867

    摘要： A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into the barrier material layer, and implanting a second alloy element after deposition of the via material. The implanted first alloy element makes the barrier material layer more resistant to copper diffusion. The implanted second alloy element diffuses to a top interface of the via material and reduces bulk diffusion from the via material.

    摘要翻译： 一种制造集成电路的方法可以包括沿着侧壁和形成通孔的底部形成阻挡材料层，所述通孔被配置为接收电连接第一导电层和第二导电层的通孔材料，注入第一合金 元件进入阻挡材料层，以及在沉积通孔材料之后注入第二合金元件。 植入的第一合金元素使得阻挡材料层更能抵抗铜扩散。 植入的第二合金元件扩散到通孔材料的顶部界面并且减小从通孔材料的体积扩散。

    Use of an existing product map as a background for making test masks
    24.
    发明授权
    Use of an existing product map as a background for making test masks 失效
    使用现有的产品图作为测试口罩的背景

    公开(公告)号：US06279147B1

    公开(公告)日：2001-08-21

    申请号：US09540365

    申请日：2000-03-31

    申请人： Matthew S. Buynoski ,  Ramkumar Subramanian ,  Todd Lukanc

    发明人： Matthew S. Buynoski ,  Ramkumar Subramanian ,  Todd Lukanc

    IPC分类号： G03F900

    CPC分类号： H01L22/34 ,  G03F1/44

    摘要： One aspect of the present invention relates to a method of making a test mask, involving the steps of providing an existing product mask pattern having a first pattern thereon; removing a portion of the first pattern from the existing product mask pattern; and forming a test pattern in the portion of the existing product mask pattern to provide the test mask, wherein the first pattern of the existing product mask pattern is substantially similar in at least one of pattern density, pattern variability, pattern size, pattern shape, preferential direction, and pattern scribe with the test pattern. Another aspect of the present invention relates to a test mask, containing a wall paper portion comprising a first pattern from an existing product mask pattern; and a test portion comprising a test pattern, wherein the first pattern of the existing product mask pattern is substantially similar in at least one of pattern density, pattern variability, pattern size, pattern shape, preferential direction, and pattern scribe with the test pattern.

    摘要翻译： 本发明的一个方面涉及一种制造测试掩模的方法，包括以下步骤：提供其上具有第一图案的现有产品掩模图案; 从现有产品掩模图案中去除第一图案的一部分; 并且在现有产品掩模图案的部分中形成测试图案以提供测试掩模，其中现有产品掩模图案的第一图案在图案密度，图案变化性，图案尺寸，图案形状中的至少一个中基本相似， 优先方向和模式划线与测试模式。 本发明的另一方面涉及一种测试掩模，其包含墙纸部分，其包含来自现有产品掩模图案的第一图案; 以及包括测试图案的测试部分，其中现有产品掩模图案的第一图案在图案密度，图案变化性，图案尺寸，图案形状，优先方向和具有测试图案的图案划线中的至少一个中基本相似。

    Silicon on insulator field effect transistor with heterojunction gate
    25.
    发明授权
    Silicon on insulator field effect transistor with heterojunction gate 有权

    公开(公告)号：US07105421B1

    公开(公告)日：2006-09-12

    申请号：US10835438

    申请日：2004-04-29

    申请人： Qi Xiang ,  Matthew S. Buynoski

    发明人： Qi Xiang ,  Matthew S. Buynoski

    IPC分类号： H01L21/00

    CPC分类号： H01L29/78696 ,  H01L29/432 ,  H01L29/66772 ,  H01L29/78645

    摘要： A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and the drain region are heavily dopes with the first impurity. A gate and a back gate are positioned along the side of the channel region and extending from the source region and is implanted with a second semiconductor with an energy gap greater than silicon and is implanted with an impurity to increase free carrier flow of a second type.

    Silicon on insulator field effect transistor with heterojunction gate
    27.
    发明授权
    Silicon on insulator field effect transistor with heterojunction gate 有权
    具有异质结栅的绝缘体上的场效应晶体管

    公开(公告)号：US06759308B2

    公开(公告)日：2004-07-06

    申请号：US09902429

    申请日：2001-07-10

    申请人： Qi Xiang ,  Matthew S. Buynoski

    发明人： Qi Xiang ,  Matthew S. Buynoski

    IPC分类号： H01L2130

    CPC分类号： H01L29/78696 ,  H01L29/432 ,  H01L29/66772 ,  H01L29/78645

    摘要： A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region is lightly doped with a first impurity to increase free carrier conductivity of a first type. The source region and the drain region are heavily dopes with the first impurity. A gate and a back gate are positioned along the side of the channel region and extending from the source region and is implanted with a second semiconductor with an energy gap greater than silicon and is implanted with an impurity to increase free carrier flow of a second type.

    摘要翻译： 在隔离掩埋氧化物层上方的薄硅层中的绝缘体上硅（SOI）衬底上形成场效应晶体管（FET）。 沟道区域被轻掺杂第一杂质以增加第一类型的自由载流子导电性。 源极区和漏极区是具有第一杂质的重掺杂物。 栅极和背栅极沿着沟道区域的侧面定位并且从源极区域延伸并且注入具有大于硅的能隙的第二半导体，并且注入杂质以增加第二类型的自由载流子 。

    Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process
    29.
    发明授权
    Metal gate with PVD amorphous silicon layer having implanted dopants for CMOS devices and method of making with a replacement gate process 有权
    具有用于CMOS器件的注入掺杂剂的PVD非晶硅层的金属栅极和用替代栅极工艺制造的方法

    公开(公告)号：US06589866B1

    公开(公告)日：2003-07-08

    申请号：US09691226

    申请日：2000-10-19

    申请人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

    发明人： Paul R. Besser ,  Qi Xiang ,  Matthew S. Buynoski

    IPC分类号： H01L2144

    CPC分类号： H01L29/66545 ,  H01L21/28052 ,  H01L29/4933

    摘要： A semiconductor structure and method for making the same provides a metal gate on a silicon substrate. The gate includes a high dielectric constant on the substrate, and a physical vapor deposited (PVD) layer of amorphous silicon on the high k gate dielectric. The metal is then formed on the PVD amorphous silicon layer. Additional dopants are implanted into the PVD amorphous silicon layer. An annealing process forms silicide in the gate, with a layer of silicon remaining unreacted. The work function of the metal gate is substantially the same as a polysilicon gate due to the presence of the PVD amorphous silicon layer, while the additional doping of the PVD amorphous silicon layer lowers the resistivity of the gate electrode.

    摘要翻译： 半导体结构及其制造方法在硅衬底上提供金属栅极。 栅极在衬底上包括高介电常数，以及在高k栅极电介质上的非晶硅的物理气相沉积（PVD）层。 然后在PVD非晶硅层上形成金属。 另外的掺杂剂被注入到PVD非晶硅层中。 退火工艺在栅极中形成硅化物，其中一层硅残留未反应。 由于PVD非晶硅层的存在，金属栅极的功函数与多晶硅栅极基本相同，而PVD非晶硅层的附加掺杂降低了栅电极的电阻率。

    Linerless shallow trench isolation method
    30.
    发明授权
    Linerless shallow trench isolation method 失效
    无缝浅沟隔离法

    公开(公告)号：US06534379B1

    公开(公告)日：2003-03-18

    申请号：US10051698

    申请日：2002-01-18

    申请人： Philip Fisher ,  Ming-Ren Lin ,  Matthew S. Buynoski

    发明人： Philip Fisher ,  Ming-Ren Lin ,  Matthew S. Buynoski

    IPC分类号： H01L2176

    CPC分类号： H01L21/76264 ,  H01L21/76283

    摘要： A method of making a semiconductor device and a method of isolation of active islands on a silicon-on-insulator semiconductor device, comprising the steps of providing a silicon-on-insulator semiconductor wafer having a silicon active layer, a dielectric isolation layer and a silicon substrate, in which the silicon active layer is formed on the dielectric isolation layer and the dielectric isolation layer is formed on the silicon substrate; forming an isolation trench, the isolation trench defining an active island in the silicon active layer; rounding at least one corner in the active island by application of a high RF bias power high density plasma; and filling the isolation trench with a dielectric trench isolation material by application of a low RF bias power high density plasma. In one embodiment, the rounding step comprises application of a HDP under etching conditions, and the filling step comprises application of a HDP under deposition conditions.

    摘要翻译： 一种制造半导体器件的方法以及在绝缘体上硅半导体器件上隔离有源岛的方法，包括以下步骤：提供具有硅有源层，介电隔离层和绝缘体隔离层的绝缘体上半导体晶片， 在硅衬底上形成硅介质隔离层上的硅有源层和电介质隔离层的硅衬底; 形成隔离沟槽，所述隔离沟槽在所述硅有源层中限定有源岛; 通过应用高RF偏置功率的高密度等离子体使活动岛中的至少一个角落四舍五入; 以及通过施加低RF偏置功率的高密度等离子体，用绝缘沟槽隔离材料填充隔离沟槽。 在一个实施例中，舍入步骤包括在蚀刻条件下施加HDP，并且填充步骤包括在沉积条件下施加HDP。