公开(公告)号：US20090272960A1

公开(公告)日：2009-11-05

申请号：US12114096

申请日：2008-05-02

申请人： Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

发明人： Bhaskar Srinivasan ,  Gurtej Sandhu ,  John Smythe

IPC分类号： H01L45/00

CPC分类号： H01L45/04 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

摘要： A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The first conductive electrode has an elevationally outermost surface and opposing laterally outermost edges at the elevationally outermost surface in one planar cross section. Multi-resistive state metal oxide-comprising material is formed over the first conductive electrode. Conductive material is deposited over the multi-resistive state metal oxide-comprising material. A second conductive electrode of the memory cell which comprises the conductive material is received over the multi-resistive state metal oxide-comprising material. The forming thereof includes etching through the conductive material to form opposing laterally outermost conductive edges of said conductive material in the one planar cross section at the conclusion of said etching which are received laterally outward of the opposing laterally outermost edges of the first conductive electrode in the one planar cross section.

摘要翻译： 形成非易失性电阻氧化物存储单元的方法包括：形成存储单元的第一导电电极作为衬底的一部分。 第一导电电极在一个平面横截面中具有垂直最外表面和在最外表面处的相对的横向最外边缘。 在第一导电电极上形成包含多电阻态金属氧化物的材料。 导电材料沉积在多电阻状态的含金属氧化物的材料上。 包含导电材料的存储单元的第二导电电极被接收在多电阻状态的含金属氧化物的材料上。 其形成包括通过导电材料的蚀刻，以在所述蚀刻结束时在一个平面截面中形成所述导电材料的相对的横向最外面的导电边缘，其在第一导电电极的相对的横向最外边缘的横向外侧接收 一个平面截面。

公开(公告)号：US20130005143A1

公开(公告)日：2013-01-03

申请号：US13616080

申请日：2012-09-14

申请人： Nishant Sinha ,  Gurtej Sandhu ,  Neil Greeley ,  John Smythe

发明人： Nishant Sinha ,  Gurtej Sandhu ,  Neil Greeley ,  John Smythe

IPC分类号： H01L21/28 ,  B82Y40/00

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap.

摘要翻译： 公开了半导体器件及其形成方法，其中至少两个相邻的导体在它们之间具有空隙绝缘体，其被绝缘材料的纳米颗粒覆盖，其尺寸是防止纳米颗粒基本上进入气隙的尺寸。

公开(公告)号：US20110201211A1

公开(公告)日：2011-08-18

申请号：US13096052

申请日：2011-04-28

申请人： Nishant Sinha ,  Gurtej Sandhu ,  Neil Greeley ,  John Smythe

发明人： Nishant Sinha ,  Gurtej Sandhu ,  Neil Greeley ,  John Smythe

IPC分类号： H01L21/31 ,  B82Y40/00

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap.

摘要翻译： 公开了半导体器件及其形成方法，其中至少两个相邻的导体在它们之间具有空隙绝缘体，其被绝缘材料的纳米颗粒覆盖，其尺寸是防止纳米颗粒基本上进入气隙的尺寸。

公开(公告)号：US20100221920A1

公开(公告)日：2010-09-02

申请号：US12781681

申请日：2010-05-17

申请人： Gurtej Sandhu ,  Mark Kiehlbauch ,  Steve Kramer ,  John Smythe

发明人： Gurtej Sandhu ,  Mark Kiehlbauch ,  Steve Kramer ,  John Smythe

IPC分类号： H01L21/311

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

摘要： Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects. The interconnects may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. The features in the selectively definable material are trimmed to desired dimensions. Spacer material is blanket deposited over the features in the selectively definable material and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed to leave a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.

摘要翻译： 公开了诸如涉及增加集成电路中的隔离特征的密度的方法。 还公开了与该方法相关联的结构。 在一个或多个实施例中，触头在其它结构（例如导电互连）的间距上形成。 互连可以由间距倍增形成。 为了形成触点，在一些实施例中，对应于一些触点的图案形成在诸如光致抗蚀剂的可选择定义的材料中。 可选择定义的材料中的特征被修剪到期望的尺寸。 间隔材料被毯子沉积在可选择定义的材料中的特征上，然后蚀刻沉积的材料以在特征的侧面留下间隔物。 去除可选择定义的材料以留下由间隔物材料限定的掩模。 由间隔物材料限定的图案可以转移到基底上，以形成间距接触。 在一些实施例中，上电触点可用于电接触衬底中的导电互连。

公开(公告)号：US08772166B2

公开(公告)日：2014-07-08

申请号：US13526792

申请日：2012-06-19

申请人： Gurtej Sandhu ,  Mark Kiehlbauch ,  Steve Kramer ,  John Smythe

发明人： Gurtej Sandhu ,  Mark Kiehlbauch ,  Steve Kramer ,  John Smythe

IPC分类号： H01L21/311

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

摘要： Methods are disclosed, including for increasing the density of isolated features in an integrated circuit. Also disclosed are associated structures. In some embodiments, contacts are formed on pitch with other structures, such as conductive interconnects that may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. Features in the selectively definable material are trimmed, and spacer material is blanket deposited over the features and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed, leaving a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.

摘要翻译： 公开了包括用于增加集成电路中的隔离特征的密度的方法。 还公开了相关联的结构。 在一些实施例中，触点是与其他结构形成的，例如可以由间距倍增形成的导电互连。 为了形成触点，在一些实施例中，对应于一些触点的图案形成在诸如光致抗蚀剂的可选择定义的材料中。 在可选择定义的材料中的特征被修整，并且间隔物材料被毯子沉积在特征上，然后蚀刻沉积的材料以在特征的侧面留下间隔物。 去除可选择定义的材料，留下由间隔物材料限定的掩模。 由间隔物材料限定的图案可以转移到基底上，以形成间距接触。 在一些实施例中，上电触点可用于电接触衬底中的导电互连。

公开(公告)号：US08298964B2

公开(公告)日：2012-10-30

申请号：US13096052

申请日：2011-04-28

申请人： Nishant Sinha ,  Gurtej Sandhu ,  Neil Greeley ,  John Smythe

发明人： Nishant Sinha ,  Gurtej Sandhu ,  Neil Greeley ,  John Smythe

IPC分类号： H01L21/31

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap.

摘要翻译： 公开了半导体器件及其形成方法，其中至少两个相邻的导体在它们之间具有空隙绝缘体，其被绝缘材料的纳米颗粒覆盖，其尺寸是防止纳米颗粒基本上进入气隙的尺寸。

公开(公告)号：US08211803B2

公开(公告)日：2012-07-03

申请号：US12781681

申请日：2010-05-17

申请人： Gurtej Sandhu ,  Mark Kiehlbauch ,  Steve Kramer ,  John Smythe

发明人： Gurtej Sandhu ,  Mark Kiehlbauch ,  Steve Kramer ,  John Smythe

IPC分类号： H01L21/311

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

摘要： Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects. The interconnects may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. The features in the selectively definable material are trimmed to desired dimensions. Spacer material is blanket deposited over the features in the selectively definable material and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed to leave a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.

摘要翻译： 公开了诸如涉及增加集成电路中的隔离特征的密度的方法。 还公开了与该方法相关联的结构。 在一个或多个实施例中，触头在其它结构（例如导电互连）的间距上形成。 互连可以由间距倍增形成。 为了形成触点，在一些实施例中，对应于一些触点的图案形成在诸如光致抗蚀剂的可选择定义的材料中。 可选择定义的材料中的特征被修剪到期望的尺寸。 间隔材料被毯子沉积在可选择定义的材料中的特征上，然后蚀刻沉积的材料以在特征的侧面留下间隔物。 去除可选择定义的材料以留下由间隔物材料限定的掩模。 由间隔物材料限定的图案可以转移到基底上，以形成间距接触。 在一些实施例中，上电触点可用于电接触衬底中的导电互连。

公开(公告)号：US20090115064A1

公开(公告)日：2009-05-07

申请号：US11933664

申请日：2007-11-01

申请人： Gurtej Sandhu ,  Mark Kiehlbauch ,  Steve Kramer ,  John Smythe

发明人： Gurtej Sandhu ,  Mark Kiehlbauch ,  Steve Kramer ,  John Smythe

IPC分类号： H01L23/52 ,  H01L21/311

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

摘要： Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects. The interconnects may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. The features in the selectively definable material are trimmed to desired dimensions. Spacer material is blanket deposited over the features in the selectively definable material and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed to leave a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.

摘要翻译： 公开了诸如涉及增加集成电路中的隔离特征的密度的方法。 还公开了与该方法相关联的结构。 在一个或多个实施例中，触头在其它结构（例如导电互连）的间距上形成。 互连可以由间距倍增形成。 为了形成触点，在一些实施例中，对应于一些触点的图案形成在诸如光致抗蚀剂的可选择定义的材料中。 可选择定义的材料中的特征被修剪到期望的尺寸。 间隔材料被毯子沉积在可选择定义的材料中的特征上，然后蚀刻沉积的材料以在特征的侧面留下间隔物。 去除可选择定义的材料以留下由间隔物材料限定的掩模。 由间隔物材料限定的图案可以转移到基底上，以形成间距接触。 在一些实施例中，上电触点可用于电接触衬底中的导电互连。

公开(公告)号：US20070210366A1

公开(公告)日：2007-09-13

申请号：US11369236

申请日：2006-03-07

申请人： Gurtej Sandhu ,  John Smythe

发明人： Gurtej Sandhu ,  John Smythe

IPC分类号： H01L21/8244

CPC分类号： H01L21/76237 ,  G11C11/401 ,  H01L27/10844 ,  H01L27/11517

摘要： Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material. Embodiments further include methods of fabricating the trench structures with the implant of energetic species to the predetermined depth. In various embodiments the implant of energetic species is used to densify the dielectric material to provide a uniform wet etch rate across the surface of the dielectric material. Embodiments also include memory devices, integrated circuits, and electronic systems that include shallow trench isolation structures having the dielectric material with the high flux of energetic species implanted to the predetermined depth of the dielectric material.

摘要翻译： 本公开的实施例包括浅沟槽隔离结构，其具有将能量物质注入电介质材料的预定深度的电介质材料。 实施例还包括使能量物质的植入物到预定深度制造沟槽结构的方法。 在各种实施例中，能量物质的注入用于致密化电介质材料，以提供穿过电介质材料表面的均匀的湿蚀刻速率。 实施例还包括存储器件，集成电路和电子系统，其包括浅沟槽隔离结构，其具有植入到介电材料的预定深度的高能量物质的高通量的电介质材料。

公开(公告)号：US20130005080A1

公开(公告)日：2013-01-03

申请号：US13608992

申请日：2012-09-10

申请人： John Smythe ,  Bhaskar Srinivasan ,  Ming Zhang

发明人： John Smythe ,  Bhaskar Srinivasan ,  Ming Zhang

IPC分类号： H01L21/26 ,  H01L21/44 ,  H01L21/06

CPC分类号： H01L29/66136 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823425 ,  H01L21/823814 ,  H01L27/10873 ,  H01L27/24 ,  H01L29/665 ,  H01L29/6659

摘要： Some embodiments include methods in which microwave radiation is used to activate dopant and/or increase crystallinity of semiconductor material during formation of a semiconductor construction. In some embodiments, the microwave radiation has a frequency of about 5.8 gigahertz, and a temperature of the semiconductor construction does not exceed about 500° C. during the exposure to the microwave radiation.

摘要翻译： 一些实施例包括在形成半导体结构期间使用微波辐射来激活掺杂剂和/或增加半导体材料的结晶度的方法。 在一些实施例中，微波辐射具有约5.8千兆赫的频率，并且在暴露于微波辐射期间半导体构造的温度不超过约500℃。