公开(公告)号：US20050221109A1

公开(公告)日：2005-10-06

申请号：US10815734

申请日：2004-04-02

申请人： Taiji Torigoe ,  Kazutaka Mori ,  Sunao Aoki ,  Kouji Takahashi ,  Minoru Ohara

发明人： Taiji Torigoe ,  Kazutaka Mori ,  Sunao Aoki ,  Kouji Takahashi ,  Minoru Ohara

IPC分类号： B32B15/04 ,  C23C4/10 ,  C23C28/00

CPC分类号： C23C4/11 ,  B32B15/04 ,  C23C28/3215 ,  C23C28/3455 ,  F05B2230/90 ,  F05C2253/12 ,  Y02T50/67 ,  Y10T428/12618

摘要： A thermal barrier coating enabling to prevent peeling of layer in a high temperature use and still having a high thermal barrier effect, a turbine part coated by this thermal barrier coating and a gas turbine comprising this turbine part are provided. The thermal barrier coating comprises a base material 21 of high temperature heat resistant alloy and a ceramics layer 23 formed on the base material 21. The ceramics layer 23 comprises ZrO2 added with Yb2O3 as stabilizer and is laminated on the base material via a bond coat layer 22 laminated as a metallic bond layer. A plurality of cracks 23A are preferably introduced in the ceramics layer 23. The turbine part is constructed having its surface coated with the above thermal barrier coating.

摘要翻译： 提供能够防止在高温使用中并且仍然具有高热障效应的层的剥离的热障涂层，由该热障涂层涂覆的涡轮部分和包括该涡轮部的燃气轮机。 隔热涂层包括高温耐热合金的基材21和形成在基材21上的陶瓷层23。 陶瓷层23包含添加有Yb 2 O 3 O 3的稳定剂的ZrO 2，并且通过层压的粘合涂层22层压在基材上 作为金属结合层。 在陶瓷层23中优选引入多个裂纹23A。 涡轮机部件被构造成具有涂覆有上述热障涂层的表面。

公开(公告)号：US5657264A

公开(公告)日：1997-08-12

申请号：US159256

申请日：1993-11-30

申请人： Tatsumi Yamauchi ,  Masahiro Iwamura ,  Kazutaka Mori

发明人： Tatsumi Yamauchi ,  Masahiro Iwamura ,  Kazutaka Mori

IPC分类号： G11C7/12 ,  G11C11/419 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C11/419

摘要： A semiconductor memory comprises a write driver which is provided to correspond to respective data line and by which data lines connected with a memory cell through the control of a word line are driven in a write operation. The write driver includes MOSFETs of first group and MOSFETs of second group. In a case where a write enable signal does not designate the write operation, the MOSFETs of the first group are normally in ON states to pull up the data lines. Besides, in a case where the write enable signal designates the write operation, each of them operates in accordance with the value of input data, to maintain the ON states and pull up the corresponding data line in case of driving the data line to a "high" level and to fall into OFF states in case of driving the data line to a "low" level. On the other hand, the MOSFETs of the second group are normally in OFF states. Besides, in the case where the write enable signal designates the write operation, each of them operates in accordance with the value of the input data, to fall into ON state and draw the corresponding data line to the low level in the case of driving the data lines to the low level.

摘要翻译： 半导体存储器包括写驱动器，其被提供以对应于相应的数据线，并且通过字线的控制与存储器单元连接的数据线在写入操作中被驱动。 写驱动器包括第一组的MOSFET和第二组的MOSFET。 在写入使能信号不表示写入操作的情况下，第一组的MOSFET通常处于ON状态以上拉数据线。 此外，在写入使能信号指定写入操作的情况下，它们中的每一个根据输入数据的值进行操作，以在将数据线驱动到“ 高“电平并且在将数据线驱动到”低“电平的情况下落入OFF状态。 另一方面，第二组的MOSFET通常处于OFF状态。 此外，在写入使能信号指定写入操作的情况下，它们中的每一个根据输入数据的值进行操作以进入ON状态，并且在驱动该操作的情况下将相应的数据线绘制到低电平 数据线到低电平。

公开(公告)号：US07859100B2

公开(公告)日：2010-12-28

申请号：US11301339

申请日：2005-12-13

申请人： Taiji Torigoe ,  Ikuo Okada ,  Katsumi Namba ,  Kazutaka Mori ,  Wei Pan ,  Qiang Xu

发明人： Taiji Torigoe ,  Ikuo Okada ,  Katsumi Namba ,  Kazutaka Mori ,  Wei Pan ,  Qiang Xu

IPC分类号： H01L23/06

CPC分类号： F01D5/288 ,  C23C4/11 ,  C23C28/3215 ,  C23C28/3455 ,  C23C30/00 ,  F05D2230/90 ,  F05D2300/611 ,  Y02T50/67 ,  Y02T50/672

摘要： Provided are a thermal barrier coating material and a member coated with thermal barrier that can suppress the separation when used at a high temperature, and have a high thermal barrier effect; a method for manufacturing the member coated with thermal barrier; a turbine member coated with the thermal barrier coating material; and a gas turbine. More specifically provided are a shield coating member comprising a heat-resistant substrate, a bond coat layer formed on the heat-resistant substrate, and a ceramic layer formed on the bond coat layer, wherein the ceramic layer comprises a ceramic represented by a general formula A2Zr2O7, wherein A denotes a rare earth element, and the ceramic layer has (a) a porosity of 1 to 30%, (b) cracks in a thickness direction in pitches of 5 to 100% the total thickness of layers other than the bond coat layer on the heat-resistant substrate, or (c) columnar crystals.

摘要翻译： 提供了一种隔热涂层材料和涂有热障的构件，其可以在高温下使用时抑制分离，并且具有高的隔热效果; 制造涂有热障的部件的方法; 涂有所述热障涂层材料的涡轮机构件; 和燃气轮机。 更具体地提供了一种屏蔽涂层构件，其包括耐热衬底，形成在耐热衬底上的接合涂层和形成在接合涂层上的陶瓷层，其中陶瓷层包括由通式 A2Zr2O7，其中A表示稀土元素，陶瓷层具有（a）孔隙率为1〜30％，（b）厚度方向的间距的裂纹为除粘结以外的层的总厚度的5〜100％ 涂层在耐热基材上，或（c）柱状晶体。

公开(公告)号：US07354663B2

公开(公告)日：2008-04-08

申请号：US10815734

申请日：2004-04-02

申请人： Taiji Torigoe ,  Kazutaka Mori ,  Sunao Aoki ,  Kouji Takahashi ,  Minoru Ohara

发明人： Taiji Torigoe ,  Kazutaka Mori ,  Sunao Aoki ,  Kouji Takahashi ,  Minoru Ohara

IPC分类号： B32B9/00

CPC分类号： C23C4/11 ,  B32B15/04 ,  C23C28/3215 ,  C23C28/3455 ,  F05B2230/90 ,  F05C2253/12 ,  Y02T50/67 ,  Y10T428/12618

摘要： A thermal barrier coating enabling to prevent peeling of layer in a high temperature use and still having a high thermal barrier effect, a turbine part coated by this thermal barrier coating and a gas turbine comprising this turbine part are provided. The thermal barrier coating comprises a base material 21 of high temperature heat resistant alloy and a ceramics layer 23 formed on the base material 21. The ceramics layer 23 comprises ZrO2 added with Yb2O3 as stabilizer and is laminated on the base material via a bond coat layer 22 laminated as a metallic bond layer. A plurality of cracks 23A are preferably introduced in the ceramics layer 23. The turbine part is constructed having its surface coated with the above thermal barrier coating.

摘要翻译： 提供能够防止在高温使用中并且仍然具有高热障效应的层的剥离的热障涂层，由该热障涂层涂覆的涡轮部分和包括该涡轮部的燃气轮机。 隔热涂层包括高温耐热合金的基材21和形成在基材21上的陶瓷层23。 陶瓷层23由添加了Yb 2 O 3 O 3的稳定剂构成的ZrO 2 2层叠在基材上，层叠有粘接层22 作为金属结合层。 在陶瓷层23中优选引入多个裂纹23A。 涡轮机部件被构造成具有涂覆有上述热障涂层的表面。

公开(公告)号：US20080055140A1

公开(公告)日：2008-03-06

申请号：US11877561

申请日：2007-10-23

申请人： Ryusuke SAHARA ,  Mitsugu Kusunoki ,  Kazutaka Mori ,  Hiroshige Kogayu

发明人： Ryusuke SAHARA ,  Mitsugu Kusunoki ,  Kazutaka Mori ,  Hiroshige Kogayu

IPC分类号： H03M1/66

CPC分类号： H03M1/1061 ,  H03M1/687 ,  H03M1/785 ,  H03M1/808

摘要： A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.

摘要翻译： 具有包括多个第一存储单元的存储器垫的DAC和连接到多个第一存储单元的多个输出线。 多个存储单元中的每一个具有包括双极晶体管的第一存储器部分，并且基于双极晶体管的结是否被破坏来存储非易失性的信息，以及连接到第一存储器部分并用于输出的第二存储器部分 信息到多个输出行中的相应一个。 DAC具有第一模式，其中当信息被写入第二存储器部分时，信息从第一存储器部分传送到第二存储器部分，以及第二模式，其中第二存储器部分被外部指定并且信息被写入 第二存储器部分。 因此，可以提高D / A转换器的性能。

公开(公告)号：US07310266B2

公开(公告)日：2007-12-18

申请号：US11409963

申请日：2006-04-25

申请人： Ryusuke Sahara ,  Mitsugu Kusunoki ,  Kazutaka Mori ,  Hiroshige Kogayu

发明人： Ryusuke Sahara ,  Mitsugu Kusunoki ,  Kazutaka Mori ,  Hiroshige Kogayu

IPC分类号： G11C11/40 ,  H03M1/66

CPC分类号： H03M1/1061 ,  H03M1/687 ,  H03M1/785 ,  H03M1/808

摘要： A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions.

摘要翻译： 具有包括多个第一存储单元的存储器垫的DAC和连接到多个第一存储单元的多个输出线。 多个存储单元中的每一个具有包括双极晶体管的第一存储器部分，并且基于双极晶体管的结点是否被破坏来存储非易失性的信息，以及连接到第一存储器部分并用于输出的第二存储器部分 信息到多个输出行中的相应一个。 DAC具有第一模式，其中当信息被写入第二存储器部分时，信息从第一存储器部分传送到第二存储器部分，以及第二模式，其中第二存储器部分被外部指定并且信息被写入 第二存储器部分。

公开(公告)号：US06937068B2

公开(公告)日：2005-08-30

申请号：US10642138

申请日：2003-08-18

申请人： Michiaki Nakayama ,  Masato Hamamoto ,  Kazutaka Mori ,  Satoru Isomura

发明人： Michiaki Nakayama ,  Masato Hamamoto ,  Kazutaka Mori ,  Satoru Isomura

IPC分类号： H01L27/092 ,  H01L27/11 ,  H01L27/04

CPC分类号： H01L27/1104 ,  H01L27/0921 ,  H01L27/0928

摘要： An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.

摘要翻译： 具有CMOS电路的集成电路，其通过将n型阱2（其中CMOS电路的p沟道晶体管Tp被置位）与通过开关晶体管Tps的电源线Vdd电连接而构成，并且电连接p型阱 如图3所示，其中CMOS电路的n沟道晶体管Tn被设置，电源线Vss通过开关晶体管Tns。 当集成电路被测试时，可以通过关断开关晶体管Tps和Tns并从外部单元向n型阱2和p型阱3提供适合于测试的电位来控制由于泄漏电流引起的热失控。 通过接通开关晶体管Tps和Tns并分别将n型阱2和p型阱3分别设置为电压Vdd和Vss可以防止闩锁现象和操作速度的波动。

公开(公告)号：US5639572A

公开(公告)日：1997-06-17

申请号：US514102

申请日：1995-08-11

申请人： Kazutaka Mori ,  Hitoshi Miyamoto ,  Tsuneaki Matsudaira

发明人： Kazutaka Mori ,  Hitoshi Miyamoto ,  Tsuneaki Matsudaira

IPC分类号： C04B35/42 ,  C25B9/00 ,  C25B9/04 ,  H01B1/08 ,  H01M8/02 ,  H01M8/12 ,  H01M10/38

CPC分类号： H01B1/08 ,  C04B35/42 ,  H01M8/0215 ,  H01M8/0219

摘要： An interconnector material for use in electrochemical cells having Y.sub.2 O.sub.3 -stabilized ZrO.sub.2 as a solid electrolyte, said interconnector material comprising a lanthanum chromite material of the following general formula:(La.sub.1-x Sr.sub.x)(Cr.sub.1-y M.sub.y)O.sub.3,where M is Zr or Ti, x is in the range of 0.1 to 0.2, and y is in the range of 0.05 to 0.2.

摘要翻译： 一种用于具有Y 2 O 3稳定的ZrO 2作为固体电解质的电化学电池的互连器材料，所述互连器材料包含以下通式的（Ⅵ-xSrx）（Cr1-yMy）O3，其中M是Zr或Ti ，x在0.1〜0.2的范围内，y在0.05〜0.2的范围内。

公开(公告)号：US5362998A

公开(公告)日：1994-11-08

申请号：US193643

申请日：1994-02-07

申请人： Masahiro Iwamura ,  Hideo Maejima ,  Atsuo Watanabe ,  Kazutaka Mori

发明人： Masahiro Iwamura ,  Hideo Maejima ,  Atsuo Watanabe ,  Kazutaka Mori

IPC分类号： H01L27/06 ,  H01L21/8249 ,  H03K17/56 ,  H03K17/567 ,  H03K19/013 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/02

CPC分类号： H03K19/0136 ,  H03K19/09448

摘要： A composite circuit device of bipolar transistors and MOS transistors has a series connection of an NPN transistor for pull-up and a PNP transistor for pull-down. The composite circuit device has independent base drive circuits so provided that the base of the NPN transistor for pull-up is electrically isolated from the base of the PNP transistor for pull-down during the on-off switching operation. The composite circuit device is also provided with base precharge circuitry for pre-charging the base of the PNP transistor during the off operation state thereof. A composite circuit is also provided with circuitry for enhancing the turn-on switching speed of the pull-down PNP transistor. Additionally, a composite circuit of bipolar transistors and MOS transistors is constituted by a switch having a high input impedance and low on-resistance which can be applied as a component of an electronic circuit.

摘要翻译： 双极晶体管和MOS晶体管的复合电路器件具有用于上拉的NPN晶体管和用于下拉的PNP晶体管的串联连接。 复合电路器件具有独立的基极驱动电路，使得用于上拉的NPN晶体管的基极与PNP晶体管的基极电隔离，用于在截止开关操作期间进行下拉。 复合电路器件还设置有用于在其关断操作状态期间对PNP晶体管的基极进行预充电的基极预充电电路。 复合电路还提供有用于增强下拉PNP晶体管的导通开关速度的电路。 此外，双极晶体管和MOS晶体管的复合电路由具有高输入阻抗和低导通电阻的开关构成，其可以用作电子电路的组件。

公开(公告)号：US5285414A

公开(公告)日：1994-02-08

申请号：US765838

申请日：1991-09-26

申请人： Tatsumi Yamauchi ,  Masahiro Iwamura ,  Kazutaka Mori

发明人： Tatsumi Yamauchi ,  Masahiro Iwamura ,  Kazutaka Mori

IPC分类号： G11C7/12 ,  G11C11/419 ,  G11C11/40

CPC分类号： G11C7/12 ,  G11C11/419

摘要： A semiconductor memory comprises a write driver which is provided to correspond to respective data line and by which data lines connected with a memory cell through the control of a word line are driven in a write operation. The write driver includes MOSFETs of first group and MOSFETs of second group. In a case where a write enable signal does not designate the write operation, the MOSFETs of the first group are normally in ON states to pull up the data lines. Besides, in a case where the write enable signal designates the write operation, each of them operates in accordance with the value of input data, to maintain the ON states and pull up the corresponding data line in case of driving the data line to a "high" level and to fall into OFF states in case of driving the data line to a "low" level. On the other hand, the MOSFETs of the second group are normally in OFF states. Besides, in the case where the write enable signal designates the write operation, each of them operates in accordance with the value of the input data, to fall into ON state and draw the corresponding data line to the low level in the case of driving the data lines to the low level.

摘要翻译： 半导体存储器包括写驱动器，其被提供以对应于相应的数据线，并且通过字线的控制与存储器单元连接的数据线在写入操作中被驱动。 写驱动器包括第一组的MOSFET和第二组的MOSFET。 在写入使能信号不表示写入操作的情况下，第一组的MOSFET通常处于ON状态以上拉数据线。 此外，在写入使能信号指定写入操作的情况下，它们中的每一个根据输入数据的值进行操作，以在将数据线驱动到“ 高“电平并且在将数据线驱动到”低“电平的情况下落入OFF状态。 另一方面，第二组的MOSFET通常处于OFF状态。 此外，在写入使能信号指定写入操作的情况下，它们中的每一个根据输入数据的值进行操作以进入ON状态，并且在驱动该操作的情况下将相应的数据线绘制到低电平 数据线到低电平。