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    Composite circuit of bipolar transistors and MOS transistors and semiconductor integrated circuit device using the same
    1.
    发明授权
    Composite circuit of bipolar transistors and MOS transistors and semiconductor integrated circuit device using the same 失效
    双极晶体管和MOS晶体管的复合电路和使用其的半导体集成电路器件

    公开(公告)号：US5362998A

    公开(公告)日：1994-11-08

    申请号：US193643

    申请日：1994-02-07

    申请人： Masahiro Iwamura ,  Hideo Maejima ,  Atsuo Watanabe ,  Kazutaka Mori

    发明人： Masahiro Iwamura ,  Hideo Maejima ,  Atsuo Watanabe ,  Kazutaka Mori

    IPC分类号： H01L27/06 ,  H01L21/8249 ,  H03K17/56 ,  H03K17/567 ,  H03K19/013 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/02

    CPC分类号： H03K19/0136 ,  H03K19/09448

    摘要： A composite circuit device of bipolar transistors and MOS transistors has a series connection of an NPN transistor for pull-up and a PNP transistor for pull-down. The composite circuit device has independent base drive circuits so provided that the base of the NPN transistor for pull-up is electrically isolated from the base of the PNP transistor for pull-down during the on-off switching operation. The composite circuit device is also provided with base precharge circuitry for pre-charging the base of the PNP transistor during the off operation state thereof. A composite circuit is also provided with circuitry for enhancing the turn-on switching speed of the pull-down PNP transistor. Additionally, a composite circuit of bipolar transistors and MOS transistors is constituted by a switch having a high input impedance and low on-resistance which can be applied as a component of an electronic circuit.

    摘要翻译： 双极晶体管和MOS晶体管的复合电路器件具有用于上拉的NPN晶体管和用于下拉的PNP晶体管的串联连接。 复合电路器件具有独立的基极驱动电路，使得用于上拉的NPN晶体管的基极与PNP晶体管的基极电隔离，用于在截止开关操作期间进行下拉。 复合电路器件还设置有用于在其关断操作状态期间对PNP晶体管的基极进行预充电的基极预充电电路。 复合电路还提供有用于增强下拉PNP晶体管的导通开关速度的电路。 此外，双极晶体管和MOS晶体管的复合电路由具有高输入阻抗和低导通电阻的开关构成，其可以用作电子电路的组件。

    Semiconductor memory
    2.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US5657264A

    公开(公告)日：1997-08-12

    申请号：US159256

    申请日：1993-11-30

    申请人： Tatsumi Yamauchi ,  Masahiro Iwamura ,  Kazutaka Mori

    发明人： Tatsumi Yamauchi ,  Masahiro Iwamura ,  Kazutaka Mori

    IPC分类号： G11C7/12 ,  G11C11/419 ,  G11C7/00

    CPC分类号： G11C7/12 ,  G11C11/419

    摘要： A semiconductor memory comprises a write driver which is provided to correspond to respective data line and by which data lines connected with a memory cell through the control of a word line are driven in a write operation. The write driver includes MOSFETs of first group and MOSFETs of second group. In a case where a write enable signal does not designate the write operation, the MOSFETs of the first group are normally in ON states to pull up the data lines. Besides, in a case where the write enable signal designates the write operation, each of them operates in accordance with the value of input data, to maintain the ON states and pull up the corresponding data line in case of driving the data line to a "high" level and to fall into OFF states in case of driving the data line to a "low" level. On the other hand, the MOSFETs of the second group are normally in OFF states. Besides, in the case where the write enable signal designates the write operation, each of them operates in accordance with the value of the input data, to fall into ON state and draw the corresponding data line to the low level in the case of driving the data lines to the low level.

    摘要翻译： 半导体存储器包括写驱动器，其被提供以对应于相应的数据线，并且通过字线的控制与存储器单元连接的数据线在写入操作中被驱动。 写驱动器包括第一组的MOSFET和第二组的MOSFET。 在写入使能信号不表示写入操作的情况下，第一组的MOSFET通常处于ON状态以上拉数据线。 此外，在写入使能信号指定写入操作的情况下，它们中的每一个根据输入数据的值进行操作，以在将数据线驱动到“ 高“电平并且在将数据线驱动到”低“电平的情况下落入OFF状态。 另一方面，第二组的MOSFET通常处于OFF状态。 此外，在写入使能信号指定写入操作的情况下，它们中的每一个根据输入数据的值进行操作以进入ON状态，并且在驱动该操作的情况下将相应的数据线绘制到低电平 数据线到低电平。

    Semiconductor memory having transistors which drive data lines in accordance with values of write data and column select signal
    3.
    发明授权
    Semiconductor memory having transistors which drive data lines in accordance with values of write data and column select signal 失效
    具有根据写数据和列选择信号的值驱动数据线的晶体管的半导体存储器

    公开(公告)号：US5285414A

    公开(公告)日：1994-02-08

    申请号：US765838

    申请日：1991-09-26

    申请人： Tatsumi Yamauchi ,  Masahiro Iwamura ,  Kazutaka Mori

    发明人： Tatsumi Yamauchi ,  Masahiro Iwamura ,  Kazutaka Mori

    IPC分类号： G11C7/12 ,  G11C11/419 ,  G11C11/40

    CPC分类号： G11C7/12 ,  G11C11/419

    摘要： A semiconductor memory comprises a write driver which is provided to correspond to respective data line and by which data lines connected with a memory cell through the control of a word line are driven in a write operation. The write driver includes MOSFETs of first group and MOSFETs of second group. In a case where a write enable signal does not designate the write operation, the MOSFETs of the first group are normally in ON states to pull up the data lines. Besides, in a case where the write enable signal designates the write operation, each of them operates in accordance with the value of input data, to maintain the ON states and pull up the corresponding data line in case of driving the data line to a "high" level and to fall into OFF states in case of driving the data line to a "low" level. On the other hand, the MOSFETs of the second group are normally in OFF states. Besides, in the case where the write enable signal designates the write operation, each of them operates in accordance with the value of the input data, to fall into ON state and draw the corresponding data line to the low level in the case of driving the data lines to the low level.

    摘要翻译： 半导体存储器包括写驱动器，其被提供以对应于相应的数据线，并且通过字线的控制与存储器单元连接的数据线在写入操作中被驱动。 写驱动器包括第一组的MOSFET和第二组的MOSFET。 在写入使能信号不表示写入操作的情况下，第一组的MOSFET通常处于ON状态以上拉数据线。 此外，在写入使能信号指定写入操作的情况下，它们中的每一个根据输入数据的值进行操作，以在将数据线驱动到“ 高“电平并且在将数据线驱动到”低“电平的情况下落入OFF状态。 另一方面，第二组的MOSFET通常处于OFF状态。 此外，在写入使能信号指定写入操作的情况下，它们中的每一个根据输入数据的值进行操作以进入ON状态，并且在驱动该操作的情况下将相应的数据线绘制到低电平 数据线到低电平。

    Pipelined semiconductor devices suitable for ultra large scale integration
    5.
    发明授权
    Pipelined semiconductor devices suitable for ultra large scale integration 失效
    适用于超大规模集成的流水线半导体器件

    公开(公告)号：US06467004B1

    公开(公告)日：2002-10-15

    申请号：US09477448

    申请日：2000-01-04

    申请人： Masahiro Iwamura ,  Shigeya Tanaka ,  Takashi Hotta ,  Tatsumi Yamauchi ,  Kazutaka Mori

    发明人： Masahiro Iwamura ,  Shigeya Tanaka ,  Takashi Hotta ,  Tatsumi Yamauchi ,  Kazutaka Mori

    IPC分类号： G06F938

    CPC分类号： G06F9/3875 ,  G06F9/3869

    摘要： A high speed, high performance pipelined semiconductor device is provided, such as a pipelined data processing device and memory device. In the pipeline operation, a functional circuit unit and a transmission unit are separately controlled at each pipeline stage cycle. A transmission unit between two functional circuit units is divided into N transmission units while considering a cycle time, and each divided transmission unit is assigned one pipeline stage cycle.

    摘要翻译： 提供了一种高速，高性能流水线半导体器件，例如流水线数据处理设备和存储器件。 在流水线操作中，功能电路单元和传输单元在每个流水线级周期被单独控制。 两个功能电路单元之间的传输单元在考虑周期时间的同时被分成N个传输单元，并且每个划分的传输单元被分配一个流水线级周期。

    THERMAL BARRIER COATING MATERIAL
    8.
    发明申请
    THERMAL BARRIER COATING MATERIAL 审中-公开
    热障涂层材料

    公开(公告)号：US20100242797A1

    公开(公告)日：2010-09-30

    申请号：US12675307

    申请日：2009-02-03

    申请人： Ichiro Nagano ,  Taiji Torigoe ,  Katsunori Akiyama ,  Masato Shida ,  Kazutaka Mori ,  Yasuhiko Tsuru ,  Ikuo Okada

    发明人： Ichiro Nagano ,  Taiji Torigoe ,  Katsunori Akiyama ,  Masato Shida ,  Kazutaka Mori ,  Yasuhiko Tsuru ,  Ikuo Okada

    IPC分类号： C09D5/00

    CPC分类号： C23C30/00 ,  C04B35/495 ,  C04B2235/3224 ,  C04B2235/3225 ,  C04B2235/3251 ,  C04B2235/76 ,  C04B2235/9607 ,  C23C4/11 ,  C23C28/322 ,  C23C28/3455 ,  F05B2230/90 ,  Y02T50/67 ,  Y02T50/6765

    摘要： A thermal barrier coating material having a lower thermal conductivity than rare earth stabilized zirconia materials. A thermal barrier coating material comprising mainly a compound represented by composition formula (1): Ln1-xTaxO1.5+x wherein 0.13≦x≦0.24, and Ln represents one or more elements selected from the group consisting of Sc, Y and the lanthanoid elements. Also, a thermal barrier coating material comprising mainly a compound represented by composition formula (2): Ln1-xNbxO1.5+x wherein 0.13≦x≦0.24, and Ln represents one or more elements selected from the group consisting of Sc, Y and the lanthanoid elements. Also, a thermal barrier coating material comprising mainly a cubic compound having a fluorite structure represented by composition formula (3): Ln3NbO7 wherein Ln represents one or more elements selected from the group consisting of Sc, Y and the lanthanoid elements.

    摘要翻译： 一种具有比稀土稳定的氧化锆材料更低热导率的热障涂层材料。 主要由组成式（1）表示的化合物：Ln1-xTaxO1.5 + x的热障涂层材料，其中0.13＆nlE; x＆lt; lE; 0.24和Ln表示选自Sc，Y和 镧系元素。 此外，主要由组成式（2）表示的化合物：Ln1-xNbxO1.5 + x，其中0.13和n1E; x和nlE; 0.24和Ln表示选自Sc，Y的一种或多种元素的热障涂层材料 和镧系元素。 另外，主要包含由组成式（3）表示的萤石结构的立方体化合物：Ln3NbO7的热障涂层材料，其中Ln表示选自Sc，Y和镧系元素中的一种或多种元素。

    HEAT TREATMENT METHOD
    9.
    发明申请
    HEAT TREATMENT METHOD 有权
    热处理方法

    公开(公告)号：US20100221441A1

    公开(公告)日：2010-09-02

    申请号：US12377408

    申请日：2007-09-14

    申请人： Hitoshi Morimoto ,  Hidenobu Tamai ,  Yuya Fujii ,  Kazutaka Mori ,  Taiji Torigoe ,  Yasuhiko Tsuru

    发明人： Hitoshi Morimoto ,  Hidenobu Tamai ,  Yuya Fujii ,  Kazutaka Mori ,  Taiji Torigoe ,  Yasuhiko Tsuru

    IPC分类号： B05D3/02

    CPC分类号： C23C26/00 ,  C21D1/70 ,  C23C4/01 ,  C23C8/04 ,  C23C8/10

    摘要： A silicon resin (7) is applied to the outer wall (1b) of the transition piece (1) subjected to the thermal barrier coating by caulking the cooling holes (2a) provided in the inner wall (1a) by a resin (4). Then, the transition piece (1) is heated in an atmosphere furnace in order to burn or decompose the resin (4). A part of the silicon resin (7) applied to the outer wall (1b) of the transition piece (1) is decomposed or evaporated by the heating to be discharged to the atmosphere in the furnace, but a part of the silicon resin (7) remains and protects the outer wall (1b). Then, since the remaining silicon resin (7) protects the outer wall (1b), it is possible to reduce oxidization of the outer wall (1b) or an unevenness in color caused by the oxidization. Accordingly, it is possible to remarkably reduce the time required to improve an external appearance of the transition piece (1) after the ashing process for the transition piece (1). Moreover, the heat treatment method according to the present invention is not limited to the application to the ashing process for the transition piece (1), but can be applied to the whole product required to be subjected to the heat treatment.

    摘要翻译： 通过用树脂（4）铆接设置在内壁（1a）中的冷却孔（2a），将硅树脂（7）施加到经过隔热涂层的过渡件（1）的外壁（1b） 。 然后，将过渡件（1）在气氛炉中加热，以使树脂（4）燃烧或分解。 施加到过渡件（1）的外壁（1b）上的硅树脂（7）的一部分通过加热分解或蒸发，以排放到炉中的大气中，但是部分硅树脂（7） ）保留并保护外壁（1b）。 然后，由于剩余的硅树脂（7）保护外壁（1b），所以可以减少外壁（1b）的氧化或氧化引起的不均匀性。 因此，可以显着地减少在过渡件（1）的灰化处理之后改善过渡件（1）的外观所需的时间。 此外，本发明的热处理方法不限于对过渡件（1）的灰化处理的应用，而是可以应用于要进行热处理的整个产品。