公开(公告)号：US20160131711A1

公开(公告)日：2016-05-12

申请号：US14535647

申请日：2014-11-07

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa

IPC: G01R31/317

CPC classification number: G01R31/31726 ,  G01R31/31713 ,  G01R31/31727 ,  G01R31/318544

Abstract: Implementations of the present disclosure involve an apparatus and/or method for mixing high speed and low speed clock signals during structural testing of a digital integrated circuit to improve the test precision and efficiency. In particular, the apparatus and/or method allow for a testing device to perform stuck-bit testing of the circuit by releasing one or more clock cycles of a low speed clock signal. Further, without having to reset the testing of the circuit, at-speed testing of the circuit may be conducted by the testing device. In one embodiment, at-speed testing occurs by activating a mode signal associated with the circuit design that instructs one or more clock cycles from an internal clock signal to the circuit to be released. The testing device may return to stuck-bit testing at a low speed clock signal, or continue with at-speed testing using the high speed internal clock signal.

Abstract translation: 本公开的实现涉及用于在数字集成电路的结构测试期间混合高速和低速时钟信号以提高测试精度和效率的装置和/或方法。 具体地，该装置和/或方法允许测试装置通过释放低速时钟信号的一个或多个时钟周期来执行电路的卡位测试。 此外，不必重置电路的测试，电路的高速测试可以由测试装置进行。 在一个实施例中，通过激活与电路设计相关联的模式信号来进行速度测试，所述模式信号指示从内部时钟信号到被释放的电路的一个或多个时钟周期。 测试设备可以以低速时钟信号返回卡位测试，或使用高速内部时钟信号继续进行高速测试。

公开(公告)号：US20220156075A1

公开(公告)日：2022-05-19

申请号：US17648443

申请日：2022-02-02

Applicant: Oracle International Corporation

Inventor： James Lewis ,  Paul Jordan ,  Gregory Onufer ,  Ali Vahidsafa

IPC: G06F9/30 ,  G06F12/0875 ,  G06F12/0815 ,  G06F12/1027 ,  G06F9/38 ,  G06F9/48 ,  G06F3/06 ,  G06F11/20

Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

公开(公告)号：US10073139B2

公开(公告)日：2018-09-11

申请号：US14502509

申请日：2014-09-30

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa ,  Sriram Anandakumar

IPC: G01R31/317

CPC classification number: G01R31/31726 ,  G01R31/31705

Abstract: Implementations of the present disclosure involve an apparatus and/or method for performing cycle deterministic functional testing of a microprocessor or other computing design with one or more asynchronous clock domains. In general, the method/apparatus involves utilizing an observe bus within the microprocessor design to funnel data from within the chip design to an output bus. In addition, to ensure that the output from the chip is synchronized to a tester clock, the observe bus may feed the information from the observe bus to one or more first-in first-out (FIFO) data buffers. During testing, the data stored in the data buffers may be provided to the output pins of the chip at a rate synchronized to the tester clock such that the output appears to the testing apparatus as being cycle deterministic. Further, one or more mechanisms may be employed within the observe bus or circuit design to control the rate of input of data into the data buffers.

公开(公告)号：US09864604B2

公开(公告)日：2018-01-09

申请号：US14731216

申请日：2015-06-04

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa

IPC: G06F9/44 ,  G06F13/362

CPC classification number: G06F9/4401 ,  G06F13/362

Abstract: Implementations of the present disclosure involve a system and/or method for implementing a reset controller of a microprocessor or other type of computing system by connecting the reset controller to a reset controller bus or other type of general purpose bus. Through the reset bus, the reset controller signals used to generate the reset sequence of the system may be transmitted to the components of the system through a bus, rather than utilizing a direct wire connection between the components and the reset controller. The wires that comprise the reset bus may then be run to one or more components of the microprocessor design that are restarted during the reset sequence. Each of these components may also include a reset controller circuit that is designed to receive the reset control signals from the reset controller and decode the signals to determine if the received signal applies to the component.

公开(公告)号：US09746876B2

公开(公告)日：2017-08-29

申请号：US14590748

申请日：2015-01-06

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa

IPC: G06F1/04 ,  G06F1/24 ,  G06F11/00 ,  G06F1/08 ,  G06F1/12 ,  G06F1/14 ,  G06F1/10 ,  H04L7/00 ,  H04J3/06

CPC classification number: G06F1/08 ,  G06F1/10 ,  G06F1/12 ,  G06F1/14 ,  H04J3/0638 ,  H04J3/0685 ,  H04L7/0033

Abstract: Implementations of the present disclosure involve an apparatus and/or method for adjusting a counter in a computing system to account for drift of the counter value over time compared to another counter of the system. In particular, a processor of the computing system that includes a local counter component may access a counter component of another processor of the system, referred to as the reference counter. By comparing the value of the reference counter to the local counter, the processor may determine any drift that may have occurred over a period of time in the local counter. The calculated drift, or counter error, may be converted into one or more adjustments to the local counter to synchronize the local counter with the reference counter. In one embodiment, the adjustment to the local counter includes increasing the rate at which the local counter is incremented for a period of time.

公开(公告)号：US09355211B2

公开(公告)日：2016-05-31

申请号：US14511283

申请日：2014-10-10

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Yibin Xia ,  Dinesh Rajasavari Amirtharaj ,  Ali Vahidsafa ,  Alan Smith ,  Senthilkumar Diraviam ,  Mohd Jamil Mohd

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/06

Abstract: Systems, methods, and other embodiments associated with providing a unified tool for performing design constraints generation and verification for circuit designs are described. In one embodiment, the unified tool reads design data and design intent information for a circuit design. The unified tool generates physical flow elements and verification flow elements of the circuit design, together and in dependence on each other, based, at least in part, on the design data and the design intent information.

Abstract translation: 描述了与提供用于执行电路设计的设计约束生成和验证的统一工具相关联的系统，方法和其它实施例。 在一个实施例中，统一工具读取用于电路设计的设计数据和设计意图信息。 统一的工具至少部分地基于设计数据和设计意图信息，一起并相互依赖地生成电路设计的物理流程元素和验证流程元素。

公开(公告)号：US09323600B2

公开(公告)日：2016-04-26

申请号：US14486776

申请日：2014-09-15

Applicant: Oracle International Corporation

Inventor： Ramaswamy Sivaramakrishnan ,  Ali Vahidsafa ,  Aaron S. Wynn ,  Connie W. Cheung

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/16 ,  G06F12/08 ,  G06F12/12 ,  G06F9/30 ,  G06F11/20

CPC classification number: G06F11/0793 ,  G06F9/30 ,  G06F9/30047 ,  G06F11/073 ,  G06F11/1666 ,  G06F11/20 ,  G06F12/0804 ,  G06F12/0844 ,  G06F12/0891 ,  G06F12/126 ,  G06F2212/1008 ,  G06F2212/1032

Abstract: The systems and methods described herein may provide a flush-retire instruction for retiring “bad” cache locations (e.g., locations associated with persistent errors) to prevent their allocation for any further accesses, and a flush-unretire instruction for unretiring cache locations previously retired. These instructions may be implemented as hardware instructions of a processor. They may be executable by processes executing in a hyper-privileged state, without the need to quiesce any other processes. The flush-retire instruction may atomically flush a cache line implicated by a detected cache error and set a lock bit to disable subsequent allocation of the corresponding cache location. The flush-unretire instruction may atomically flush an identified cache line (if valid) and clear the lock bit to re-enable subsequent allocation of the cache location. Various bits in the encodings of these instructions may identify the cache location to be retired or unretired in terms of the physical cache structure.

Abstract translation: 本文描述的系统和方法可以提供用于退出“不良”高速缓存位置（例如，与持续错误相关联的位置）的刷新退出指令，以防止其对任何进一步访问的分配，以及用于撤销先前退休的高速缓存位置的刷新指令 。 这些指令可以被实现为处理器的硬件指令。 它们可以由以超级特权状态执行的进程执行，而不需要使任何其他进程停顿。 刷新 - 退出指令可以原子地刷新由检测到的高速缓存错误所牵连的高速缓存行，并设置锁定位以禁用对应的高速缓存位置的后续分配。 flush-unretire指令可以原子地刷新已识别的高速缓存行（如果有效）并清除锁定位以重新启用高速缓存位置的后续分配。 这些指令的编码中的各个比特可以根据物理高速缓存结构来标识要退休或未退出的高速缓存位置。

公开(公告)号：US20160091565A1

公开(公告)日：2016-03-31

申请号：US14502509

申请日：2014-09-30

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa ,  Sriram Anandakumar

IPC: G01R31/3177

CPC classification number: G01R31/31726 ,  G01R31/31705

Abstract: Implementations of the present disclosure involve an apparatus and/or method for performing cycle deterministic functional testing of a microprocessor or other computing design with one or more asynchronous clock domains. In general, the method/apparatus involves utilizing an observe bus within the microprocessor design to funnel data from within the chip design to an output bus. In addition, to ensure that the output from the chip is synchronized to a tester clock, the observe bus may feed the information from the observe bus to one or more first-in first-out (FIFO) data buffers. During testing, the data stored in the data buffers may be provided to the output pins of the chip at a rate synchronized to the tester clock such that the output appears to the testing apparatus as being cycle deterministic. Further, one or more mechanisms may be employed within the observe bus or circuit design to control the rate of input of data into the data buffers.

Abstract translation: 本公开的实现涉及用于利用一个或多个异步时钟域执行微处理器或其他计算设计的循环确定性功能测试的装置和/或方法。 通常，该方法/装置涉及利用微处理器设计中的观察总线将数据从芯片设计中转移到输出总线。 此外，为了确保芯片的输出与测试仪时钟同步，观察总线可将信息从观察总线馈送到一个或多个先进先出（FIFO）数据缓冲器。 在测试期间，可以以与测试器时钟同步的速率将存储在数据缓冲器中的数据提供给芯片的输出引脚，使得输出作为循环确定性出现在测试装置上。 此外，在观察总线或电路设计中可以采用一个或多个机制来控制数据到数据缓冲器中的输入速率。

公开(公告)号：US20150278053A1

公开(公告)日：2015-10-01

申请号：US14675271

申请日：2015-03-31

Applicant: Oracle International Corporation

Inventor： Ali Vahidsafa ,  Connie Wai Mun Cheung

IPC: G06F11/20

CPC classification number: G06F11/2094 ,  G06F3/0647 ,  G06F11/141 ,  G06F11/20 ,  G06F11/2069 ,  G06F12/0646 ,  G06F12/1036 ,  G06F2212/656

Abstract: A method for managing a failed memory module, including: receiving a first request to access a first memory address; identifying a memory module identifier (ID) from an end bit segment of the first memory address in the first request; generating, based on the memory module ID matching the failed memory module, a first revised memory address from the first memory address; and sending the first request with the first revised memory address to a memory controller for interpretation.

Abstract translation: 一种用于管理故障存储器模块的方法，包括：接收访问第一存储器地址的第一请求; 从所述第一请求中的所述第一存储器地址的结束位段识别存储器模块标识符（ID）; 基于与所述故障存储器模块匹配的存储器模块ID，从所述第一存储器地址生成第一修改的存储器地址; 并且将具有第一修改的存储器地址的第一请求发送到用于解释的存储器控​​制器。

公开(公告)号：US20150039938A1

公开(公告)日：2015-02-05

申请号：US14486776

申请日：2014-09-15

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Ramaswamy Sivaramakrishnan ,  Ali Vahidsafa ,  Aaron S. Wynn ,  Connie W. Cheung

IPC: G06F11/07 ,  G06F12/08

CPC classification number: G06F11/0793 ,  G06F9/30 ,  G06F9/30047 ,  G06F11/073 ,  G06F11/1666 ,  G06F11/20 ,  G06F12/0804 ,  G06F12/0844 ,  G06F12/0891 ,  G06F12/126 ,  G06F2212/1008 ,  G06F2212/1032

Abstract: The systems and methods described herein may provide a flush-retire instruction for retiring “bad” cache locations (e.g., locations associated with persistent errors) to prevent their allocation for any further accesses, and a flush-unretire instruction for unretiring cache locations previously retired. These instructions may be implemented as hardware instructions of a processor. They may be executable by processes executing in a hyper-privileged state, without the need to quiesce any other processes. The flush-retire instruction may atomically flush a cache line implicated by a detected cache error and set a lock bit to disable subsequent allocation of the corresponding cache location. The flush-unretire instruction may atomically flush an identified cache line (if valid) and clear the lock bit to re-enable subsequent allocation of the cache location. Various bits in the encodings of these instructions may identify the cache location to be retired or unretired in terms of the physical cache structure.

Abstract translation: 本文描述的系统和方法可以提供用于退出“不良”高速缓存位置（例如，与持续错误相关联的位置）的刷新退出指令，以防止其对任何进一步访问的分配，以及用于撤销先前退休的高速缓存位置的刷新指令 。 这些指令可以被实现为处理器的硬件指令。 它们可以由以超级特权状态执行的进程执行，而不需要使任何其他进程停顿。 刷新 - 退出指令可以原子地刷新由检测到的高速缓存错误所牵连的高速缓存行，并设置锁定位以禁用对应的高速缓存位置的后续分配。 flush-unretire指令可以原子地刷新已识别的高速缓存行（如果有效）并清除锁定位以重新启用高速缓存位置的后续分配。 这些指令的编码中的各个比特可以根据物理高速缓存结构来标识要退休或未退出的高速缓存位置。