公开(公告)号：US20050001748A1

公开(公告)日：2005-01-06

申请号：US10490875

申请日：2002-09-09

申请人： Patrick Clement ,  Nadim Khlat ,  Daniel Schwartz

发明人： Patrick Clement ,  Nadim Khlat ,  Daniel Schwartz

IPC分类号： H03M3/02 ,  H03M3/00

CPC分类号： H03M3/496

摘要： A Multi-Rate Analog-to-Digital Converter (19) is coupled to a single crystal oscillator (17) as a reference clock and has at least two separate channels arranged to sample and convert input data at two differing clock rates. Each channel derives a clock signal from the reference clock. Associated with each of the channels is a Sigma-Delta converter (10a, 10b) comprising a modulator (12), a filter (14) and a resampler (18). The modulator (12) receives input data and provides a data signal to the filter (14), which itself provides a filtered data signal to the associated data resampler. The data resampler resamples the data and provides a digital output signal. As there is sampling in the digital domain the advantages associated with signal processing, speed and low noise injection are obtained. Similarly as the output of the modulator (12) is in digital form, it can be manipulated and processed readily and with existing software.

摘要翻译： 多速率模数转换器（19）耦合到作为参考时钟的单晶振荡器（17），并且具有至少两个单独的通道，其布置成以两个不同的时钟速率对输入数据进行采样和转换。 每个通道从参考时钟导出时钟信号。 与每个通道相关联的是包括调制器（12），滤波器（14）和重采样器（18）的Σ-Δ转换器（10a，10b）。 调制器（12）接收输入数据并向滤波器（14）提供数据信号，滤波器本身将经过滤波的数据信号提供给相关联的数据重采样器。 数据重采样器重新采样数据并提供数字输出信号。 由于在数字领域中采用了与信号处理，速度和低噪声注入相关的优点。 类似地，当调制器（12）的输出是数字形式时，可以容易地和现有的软件操纵和处理调制器（12）的输出。

公开(公告)号：US20100164773A1

公开(公告)日：2010-07-01

申请号：US12293744

申请日：2006-03-23

申请人： Patrick Clement ,  Maher Kayal ,  Sergio Pesenti

发明人： Patrick Clement ,  Maher Kayal ,  Sergio Pesenti

IPC分类号： H03M3/00

CPC分类号： H03M3/48 ,  H03M1/181 ,  H03M1/20 ,  H03M3/49

摘要： An integrated circuit comprises a delta-sigma modulator incorporating a delta-sigma modulation loop having an analog-to-digital converter in a forward path and a digital-to-analog converter in a feedback path such that the ADC is arranged to receive samples of an analog input signal. The ADC is operably coupled to auto-ranging logic arranged to shift a digital output signal from the ADC representative of the analog input signal to counteract an effect of an input variation of the analog input signal. In this manner, the application of auto-ranging logic with a self-recovery technique supports a reduction of the number of comparators required in a multi-bit delta-sigma ADC.

摘要翻译： 集成电路包括并入具有正向通路中的模数转换器和反馈路径中的数模转换器的Δ-Σ调制环的Δ-Σ调制器，使得ADC被布置为接收 模拟输入信号。 ADC可操作地耦合到自动测距逻辑，其布置成从表示模拟输入信号的ADC移位数字输出信号，以抵消模拟输入信号的输入变化的影响。 以这种方式，具有自恢复技术的自动量程逻辑的应用支持减少多位Δ-ΣADC中所需的比较器的数量。

公开(公告)号：US07720454B1

公开(公告)日：2010-05-18

申请号：US11582067

申请日：2006-10-17

申请人： Patrick Clement ,  David Cousinard

发明人： Patrick Clement ,  David Cousinard

IPC分类号： H04B1/16

CPC分类号： H04B1/28 ,  H04B1/0032 ,  H04H40/18 ,  H04H2201/183

摘要： A radio frequency (RF) receiver includes an intermediate frequency (IF) mixer that generates an output signal based on mixing a hybrid in-band, on-channel (IBOC) signal with an intermediate frequency signal. An oscillator generates the intermediate frequency signal; wherein the intermediate frequency is less than a bandwidth of the IBOC signal.

摘要翻译： 射频（RF）接收机包括中频（IF）混频器，其基于混合带内同步信道（IBOC）信号和中频信号来产生输出信号。 振荡器产生中频信号; 其中中频小于IBOC信号的带宽。

公开(公告)号：US07672689B2

公开(公告)日：2010-03-02

申请号：US10433855

申请日：2001-10-22

申请人： Nadim Khlat ,  Patrick Clement

发明人： Nadim Khlat ,  Patrick Clement

IPC分类号： H04M1/00

CPC分类号： H04B1/7115 ,  H04B1/30 ,  H04B1/406

摘要： A multipath wideband communications receiver (100) having a plurality of RF signal paths (116, 136) covering different but overlapping frequency bands and a plurality of baseband signal paths (140, 150, 160, 170, 180, 190), the paths being re-configurable for sharing of the first and second paths in different ways in order to facilitate processing of received signals in different modes.Also, a rake receiver (800) employs a sigma-delta modulator arrangement (810) and programmable delays to provide fine delay adjustment. The sigma-delta modulator (810) may use sigma-delta circuitry from a sigma-delta A/D converters in a baseband paths of the receiver (100), that this may be achieved with no loss of functionality if in a particular reception configuration that sigma-delta A/D converter is not being utilized.

摘要翻译： 多径宽带通信接收机（100）具有覆盖不同但重叠的频带的多个RF信号路径（116,136）和多个基带信号路径（140,150,160,170,180,190），所述路径是 可重新配置为以不同方式共享第一和第二路径，以便于以不同模式处理接收到的信号。 此外，瑞克接收机（800）采用Σ-Δ调制器装置（810）和可编程延迟来提供精细的延迟调整。 Σ-Δ调制器（810）可以在接收机（100）的基带路径中使用来自Σ-ΔA/ D转换器的Σ-Δ电路，如果在特定的接收配置中可以实现这一点，而不损失功能 该Σ-ΔA / D转换器未被使用。

公开(公告)号：US07190293B2

公开(公告)日：2007-03-13

申请号：US10515561

申请日：2003-05-19

申请人： Patrick Clement ,  Nadim Khlat

发明人： Patrick Clement ,  Nadim Khlat

IPC分类号： H03M1/12

CPC分类号： H03M3/466 ,  H03M3/41

摘要： An arrangement (100) and method for sigma-delta analog-to-digital conversion by providing parallel translating sigma-delta analog-to-digital converters (21, 22) and summing their outputs to produce a digital output signal having a bandwidth greater than that of the first or second translating sigma-delta analog-to-digital converters (21, 22). The parallel translating sigma-delta analog-to-digital converters (21, 22) use switching sequences arranged to cancel third and fifth harmonics in the digital output signal. Orthogonality error in the switching sequences applied to the sigma-delta modulators is compensated by adjusting the phase of the signals applied to mixers (51, 52).

摘要翻译： 一种用于通过提供并行转换Σ-Δ模数转换器（21,22）并对其输出进行求和以产生具有大于或等于的带宽的数字输出信号的Σ-Δ模数转换的装置（100）和方法 第一或第二平移Σ-Δ模数转换器（21,22）的转换。 并行转换Σ-Δ模数转换器（21,22）使用布置成消除数字输出信号中的第三和第五谐波的开关序列。 通过调整施加到混合器（51,52）的信号的相位来补偿施加到Σ-Δ调制器的开关序列中的正交性误差。

公开(公告)号：US06713100B1

公开(公告)日：2004-03-30

申请号：US09617930

申请日：2000-08-16

申请人： Daniel Schmoutz ,  Patrick Clement

发明人： Daniel Schmoutz ,  Patrick Clement

IPC分类号： A23G300

CPC分类号： A23L19/105 ,  A21D13/36 ,  A21D13/38 ,  A23G1/48 ,  A23G1/54 ,  A23G3/48 ,  A23G3/54 ,  A23L19/09

摘要： A novel, nutritious confectionery product with a taste, texture and color that is particularly appealing to children is disclosed. The food product includes non-cereal vegetable solids and solid fat characterized in that the non-cereal vegetable solids are present in the form of particles in an amount of at least about 15% by weight of the total weight of the confectionery product. These particles are surrounded by the fat. The non-cereal vegetable solids are added and mixed into a continuous phase of fat to provide a shaped fat-based product upon setting.

摘要翻译： 公开了一种具有特别吸引儿童的味道，质地和颜色的新颖营养的糖果产品。 食品包括非谷物植物固体和固体脂肪，其特征在于非谷物植物固体以颗粒形式存在，其量为糖果产品总重量的至少约15重量％。 这些颗粒被脂肪包围。 将非谷物植物固体加入并混合到连续的脂肪相中，以在设定时提供成型的脂肪基产品。

公开(公告)号：US06597748B1

公开(公告)日：2003-07-22

申请号：US09980302

申请日：2001-11-28

申请人： Alex Hietala ,  Nadim Khlat ,  Patrick Clement

发明人： Alex Hietala ,  Nadim Khlat ,  Patrick Clement

IPC分类号： H04L2716

CPC分类号： H04B1/30

摘要： Apparatus 20, 30, 50, 60 for receiving a carrier signal modulated by a wanted signal, the modulated carrier signal occupying one of a plurality of channels whose central frequencies are separated from one another by a fixed frequency referred to as the channel spacing, the apparatus including a local oscillator 28 for generating first and second signals at a frequency which is not an integral multiple of half the channel spacing whereby when the received carrier signal is mixed with the first and second signals, a complex, digital Very Low Intermediate Frequency (VLIF) signal is generated in which the wanted signal is centred about a VLIF which is slightly larger than half the channel spacing.

摘要翻译： 用于接收由有用信号调制的载波信号的装置20,30,50,60，调制载波信号占据多个信道中的一个，其中心频率被称为信道间隔的固定频率， 该设备包括本地振荡器28，用于以不是信道间隔的一半的整数倍的频率产生第一和第二信号，由此当接收的载波信号与第一和第二信号混合时，复数数字非常低的中频 VLIF）信号，其中有用信号以略大于信道间隔的一半的VLIF为中心。

公开(公告)号：US4744095A

公开(公告)日：1988-05-10

申请号：US895528

申请日：1986-08-11

申请人： Jean-Francois R. Cornet ,  Patrick Clement

发明人： Jean-Francois R. Cornet ,  Patrick Clement

IPC分类号： H04B1/74 ,  H04L1/02 ,  H04L7/00

CPC分类号： H04L1/02

摘要： An arrangement ensuring the change-over of two channels through which the same digital information is conveyed with automatic data alignment over a .+-.3.5 bit range comprises for each channel an array of buffer stores operating at a write rate H.sub.i /N.sub.i (where i=1, 2), an oscillator operating at a rate H which provides reading of the buffer stores at the rate H/N and being synchronized in phase-opposition with one or the other of the write rates, and a logic comparator controlling the write rates H.sub.i /N.sub.i, the routing of the write rates to the input of the oscillator, as well as a change-over switch for the data.In the buffer store of the channel assumed to be the one whose quality degrades, the data are converted into N parallel streams at the rate H.sub.2 /N and are read at the rate H/N of the oscillator. In the other channel, the write rate of the buffer store is forced to the rate H.sub.1 /N-1, the read rate remaining unchanged, until there is a coincidence of N bits in the two channels; thereupon the data stream is switched, the write rate is locked at H.sub.1 /N and this write rate is applied to the oscillator.

摘要翻译： 确保在+/- 3.5位范围内自动数据对齐传送相同数字信息的两个通道的切换的布置包括：对于每个通道，以写入速率Hi / Ni（其中i = 1,2），以以速率H / N提供对缓冲器的读取的速率H操作的振荡器，并且与写入速率中的一个或另一个以相位对准的方式同步;以及控制写入的逻辑比较器 速率Hi / Ni，写入速率到振荡器的输入的路由，以及数据的切换开关。 在假定为质量劣化的信道的缓冲存储器中，将数据以速率H2 / N转换成N个并行流，并以振荡器的速率H / N读取。 在另一个通道中，缓冲存储器的写入速率被强制为速率H1 / N-1，读取速率保持不变，直到两个通道中存在N位一致; 随后数据流被切换，写入速率被锁定在H1 / N，并且该写入速率被施加到振荡器。