公开(公告)号：US07232733B2

公开(公告)日：2007-06-19

申请号：US10924469

申请日：2004-08-23

申请人： Ashraf W. Lotfi ,  Jian Tan

发明人： Ashraf W. Lotfi ,  Jian Tan

IPC分类号： H01L21/8222

CPC分类号： H01L21/823814 ,  H01L21/82385 ,  H01L21/823857

摘要： A method of forming an integrated circuit configured to accommodate higher voltage and low voltage devices. In one embodiment, the method of forming the integrated circuit includes forming a transistor by forming a gate over a semiconductor substrate. The method of forming the transistor also includes forming a source/drain by forming a lightly doped region adjacent a channel region recessed into the semiconductor substrate and forming a heavily doped region adjacent the lightly doped region. The method of forming the transistor further includes forming an oppositely doped well under and within the channel region, and forming a doped region between the heavily doped region and the oppositely doped well. The doped region has a doping concentration profile less than a doping concentration profile of the heavily doped region. The method of forming the integrated circuit also includes forming a driver switch of a driver on the semiconductor substrate.

摘要翻译： 一种形成集成电路的方法，其被配置为容纳更高电压和低电压的装置。 在一个实施例中，形成集成电路的方法包括通过在半导体衬底上形成栅极来形成晶体管。 形成晶体管的方法还包括通过形成与凹入半导体衬底中的沟道区相邻的轻掺杂区域并形成邻近轻掺杂区的重掺杂区来形成源极/漏极。 形成晶体管的方法还包括在沟道区内和沟道区内形成相对掺杂的阱，并在重掺杂区和相对掺杂的阱之间形成掺杂区。 掺杂区域具有小于重掺杂区域的掺杂浓度分布的掺杂浓度分布。 形成集成电路的方法还包括在半导体衬底上形成驱动器的驱动器开关。

公开(公告)号：US07190026B2

公开(公告)日：2007-03-13

申请号：US10924091

申请日：2004-08-23

申请人： Ashraf W. Lotfi ,  Jian Tan

发明人： Ashraf W. Lotfi ,  Jian Tan

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： G11C5/14

摘要： An integrated circuit employable with a power converter. In one embodiment, the integrated circuit includes a power switch of a power train of the power converter formed on a semiconductor substrate. The integrated circuit also includes a driver switch of a driver configured to provide a drive signal to the power switch and embodied in a transistor including a gate located over a channel region recessed into the semiconductor substrate. The transistor also includes a source/drain including a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The transistor further includes an oppositely doped well located under and within the channel region. The transistor still further includes a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.

摘要翻译： 具有电源转换器的集成电路。 在一个实施例中，集成电路包括形成在半导体衬底上的功率转换器的动力传动系的功率开关。 集成电路还包括驱动器的驱动器开关，该驱动器被配置为向电源开关提供驱动信号并且被实现在包括位于凹入到半导体衬底中的沟道区域上方的栅极的晶体管中。 晶体管还包括源极/漏极，其包括位于沟道区附近的轻掺杂区域和位于轻掺杂区域附近的重掺杂区域。 晶体管还包括位于沟道区域下方和沟槽区域内的相对掺杂阱。 晶体管还包括位于重掺杂区和相对掺杂阱之间的掺杂区，其具有小于重掺杂区的掺杂浓度分布的掺杂浓度分布。

公开(公告)号：US06903373B1

公开(公告)日：2005-06-07

申请号：US09448856

申请日：1999-11-23

申请人： Ashraf W. Lotfi ,  Jian Tan

发明人： Ashraf W. Lotfi ,  Jian Tan

IPC分类号： H01L29/16 ,  H01L21/04 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/06 ,  H01L27/08 ,  H01L27/092 ,  H01L29/24 ,  H01L29/78 ,  H01L29/786 ,  H01L31/0312 ,  H01L27/01

CPC分类号： H01L29/66068 ,  H01L21/8258 ,  H01L27/0688 ,  H01L29/1608 ,  H01L29/78

摘要： A lateral metal-oxide semiconductor field effect transistor (MOSFET) formed over a substrate of a semiconductor wafer, a method of manufacturing the same and a semiconductor device incorporating the MOSFET or the method. In one embodiment, the MOSFET includes a silicon carbide layer located over or withing the substrate, a gate formed on the silicon carbide layer. The MOSFET further includes source and drain regions located in the silicon carbide layer and in contact with the gate, the silicon carbide layer increasing a breakdown voltage of the MOSFET.

摘要翻译： 形成在半导体晶片的衬底上的横向金属氧化物半导体场效应晶体管（MOSFET），其制造方法以及包含MOSFET的半导体器件或方法。 在一个实施例中，MOSFET包括位于衬底上或与衬底相连的碳化硅层，形成在碳化硅层上的栅极。 MOSFET还包括位于碳化硅层中并与栅极接触的源极和漏极区域，碳化硅层增加了MOSFET的击穿电压。

公开(公告)号：US20130339966A1

公开(公告)日：2013-12-19

申请号：US13599486

申请日：2012-08-30

申请人： Xiaoqiao Meng ,  Jian Tan ,  Li Zhang

发明人： Xiaoqiao Meng ,  Jian Tan ,  Li Zhang

IPC分类号： G06F9/46

CPC分类号： G06F9/5061 ,  G06F2209/5013 ,  G06F2209/5018

摘要： Methods and arrangements for task scheduling. At least one job is assimilated from at least one node, each job comprising at least a map phase and a reduce phase, each of the map and reduce phases comprising at least one task. Progress of a map phase of at least one job is compared with progress of a reduce phase of at least one job. Launching of a task of a reduce phase of at least one job is scheduled in response to progress of the reduce phase of at least one job being less than progress of the map phase of at least one job.

公开(公告)号：US08252549B2

公开(公告)日：2012-08-28

申请号：US12625952

申请日：2009-11-25

申请人： Hongwei Hanna Rao ,  Jian Tan

发明人： Hongwei Hanna Rao ,  Jian Tan

IPC分类号： C12Q1/04

CPC分类号： C12N5/0068 ,  C12M23/20 ,  C12M25/06 ,  C12N5/0643 ,  C12N2503/00 ,  C12N2533/18 ,  C12N2533/54 ,  G01N33/582

摘要： Described herein are multi-purpose substrates composed of (1) a base coated with a calcium phosphate coating and (2) a fluorophore-labeled collagen adsorbed on the calcium phosphate coating. The multi-purpose substrates are useful in culturing and studying the activity of a variety of cells. The multi-purpose substrates described herein can be used for both solution- and image-based analysis of cultured cells. New methods for producing and using such coated substrates are also disclosed.

摘要翻译： 本文描述的是由（1）涂覆有磷酸钙涂层的基底和（2）吸附在磷酸钙涂层上的荧光团标记的胶原构成的多功能底物。 多功能底物可用于培养和研究各种细胞的活性。 本文所述的多功能底物可用于培养细胞的溶液和图像分析。 还公开了用于生产和使用这种涂覆的基材的新方法。

公开(公告)号：US20110294151A1

公开(公告)日：2011-12-01

申请号：US12846043

申请日：2010-07-29

申请人： Hongwei Hanna Rao ,  Jian Tan

发明人： Hongwei Hanna Rao ,  Jian Tan

IPC分类号： C12Q1/02 ,  C07F9/572 ,  B32B27/32 ,  B05D3/06 ,  B32B17/06 ,  B32B9/04 ,  C12M1/34 ,  B05D3/02 ,  C07F9/09 ,  B32B27/36

CPC分类号： C12N5/0068 ,  C12N5/0643 ,  C12N2533/18 ,  G01N33/533 ,  G01N33/582 ,  Y10T428/31507 ,  Y10T428/31935 ,  Y10T428/31938

摘要： Described herein are substrates composed of a base coated with a fluorophore-labeled calcium phosphate coating. The substrates are useful in culturing and studying the activity of a variety of cells. The substrates described herein can be used for both solution- and image-based analysis of cultured cells. New methods for producing and using such coated substrates are also disclosed.

摘要翻译： 本文描述的是由涂布有荧光团标记的磷酸钙涂层的基底组成的底物。 底物可用于培养和研究各种细胞的活性。 本文所述的底物可用于培养细胞的基于溶液和图像的分析。 还公开了用于生产和使用这种涂覆的基材的新方法。

公开(公告)号：US08058924B1

公开(公告)日：2011-11-15

申请号：US12361804

申请日：2009-01-29

申请人： Guo Jun Ren ,  Prasad Rau ,  Jian Tan ,  Qi Zhang

发明人： Guo Jun Ren ,  Prasad Rau ,  Jian Tan ,  Qi Zhang

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H03K19/00384 ,  G11C29/022 ,  G11C29/028 ,  G11C2029/0409 ,  H03K19/018528

摘要： A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device.

摘要翻译： 一种降低由于工艺，电压和温度（PVT）和/或其它变化原因导致的基于半导体的器件性能下降的方法和装置。 使用自适应反馈机制来感测和纠正性能下降，同时促进诸如可编程逻辑器件（PLD）之类的集成电路（IC）内的可配置性。 采用电压反馈机制来检测PVT变化，并自适应调整镜像电流参考以跟踪和基本上消除PVT变化。 可以替代地使用多于一个的电压反馈机构来检测差分装置内的基于PVT的变化，由此利用第一电​​压反馈机构来检测共模电压变化，而第二电压反馈机构产生镜像参考电流 基本上消除了共模电压变化，并促进了差动装置的对称运行。

公开(公告)号：US07839173B1

公开(公告)日：2010-11-23

申请号：US12539522

申请日：2009-08-11

申请人： Wenfeng Zhang ,  Qi Zhang ,  Jian Tan

发明人： Wenfeng Zhang ,  Qi Zhang ,  Jian Tan

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521 ,  H03K19/01714

摘要： A system for signal level shifting in an IC can include a first inverter having a first pull-up device and a pull-down device, wherein the first inverter is operable to receive an input signal having a voltage potential at a logic high that does not disable the first pull-up device. The system can include a second inverter coupled in series to an output of the first inverter, and a control module coupled to the output of the first inverter and an output of the second inverter. Prior to the input signal transitioning to the logic high, the control module is operable to decouple the input signal from the first pull-up device, disable the first pull-up device, and close a feedback loop that latches an output state of the second inverter.

摘要翻译： 用于IC中的信号电平移位的系统可以包括具有第一上拉装置和下拉装置的第一反相器，其中第一反相器可操作以接收具有不高于逻辑高的电压电位的输入信号 禁用第一个上拉设备。 该系统可以包括与第一反相器的输出串联耦合的第二反相器，以及耦合到第一反相器的输出和第二反相器的输出的控制模块。 在输入信号转换到逻辑高电平之前，控制模块可操作以将输入信号与第一上拉装置去耦，禁用第一上拉装置，并闭合锁存第二上拉装置的输出状态的反馈环路 逆变器。

公开(公告)号：US07759184B2

公开(公告)日：2010-07-20

申请号：US11805233

申请日：2007-05-22

申请人： Ashraf W. Lotfi ,  Jian Tan

发明人： Ashraf W. Lotfi ,  Jian Tan

IPC分类号： H01L21/00

CPC分类号： H01L29/7816 ,  H01L21/761 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0629 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/78 ,  H01L29/7833

摘要： A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The laterally diffused metal oxide semiconductor device further includes an oppositely doped well located under and within the channel region, and a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.

摘要翻译： 有利地体现在横向扩散的金属氧化物半导体器件中的晶体管，其具有位于凹入半导体衬底的沟道区域上方的栅极及其形成方法。 在一个实施例中，横向扩散的金属氧化物半导体器件包括具有位于沟道区附近的轻掺杂区的源极/漏极和位于轻掺杂区附近的重掺杂区。 横向扩散的金属氧化物半导体器件还包括位于沟道区之下和沟槽区内的相对掺杂的阱，以及位于重掺杂区和相对掺杂阱之间的掺杂区，其掺杂浓度分布小于掺杂浓度分布 重掺杂区域。

公开(公告)号：US07229886B2

公开(公告)日：2007-06-12

申请号：US10924461

申请日：2004-08-23

申请人： Ashraf W. Lotfi ,  Jian Tan

发明人： Ashraf W. Lotfi ,  Jian Tan

IPC分类号： H01L21/336

CPC分类号： H01L21/823892 ,  H01L21/823814 ,  H01L21/82385 ,  H01L29/1083

摘要： A method of forming an integrated circuit configured to accommodate higher voltage and low voltage devices. In one embodiment, the method of forming the integrated circuit includes forming a switch on a semiconductor substrate, and forming a driver switch of a driver embodied in a transistor. The method of forming the transistor includes forming a gate over the semiconductor substrate. The method of forming the transistor also includes forming a source/drain by forming a lightly doped region adjacent a channel region recessed into the semiconductor substrate, and forming a heavily doped region adjacent the lightly doped region. The method of forming the transistor further includes forming an oppositely doped well under and within the channel region. The method of forming the transistor still further includes forming a doped region with a doping concentration profile less than the heavily doped region between the heavily doped region and the oppositely doped well.

摘要翻译： 一种形成集成电路的方法，其被配置为容纳更高电压和低电压的装置。 在一个实施例中，形成集成电路的方法包括在半导体衬底上形成开关，以及形成体现在晶体管中的驱动器的驱动器开关。 形成晶体管的方法包括在半导体衬底上形成栅极。 形成晶体管的方法还包括通过形成与凹入半导体衬底的沟道区相邻的轻掺杂区域形成源极/漏极，以及形成邻近轻掺杂区的重掺杂区。 形成晶体管的方法还包括在沟道区内和沟槽区内形成相对掺杂的阱。 形成晶体管的方法还包括形成具有小于重掺杂区域和相对掺杂阱之间的重掺杂区域的掺杂浓度分布的掺杂区域。