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51 条记录 (耗时 0.026 秒)

    DOUBLE-RATE MEMORY
    21.
    发明申请
    DOUBLE-RATE MEMORY 有权
    双速记忆

    公开(公告)号：US20080037357A1

    公开(公告)日：2008-02-14

    申请号：US11464129

    申请日：2006-08-11

    申请人： Perry H. Pelley, III ,  George P. Hockstra

    发明人： Perry H. Pelley, III ,  George P. Hockstra

    IPC分类号： G11C8/00

    CPC分类号： G11C8/10 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18

    摘要： A double-rate memory has an array of single word line memory cells arranged in rows and columns. The single word line memory cells provide and store data via a first port. Addressing and control circuitry is coupled to the array of single word line memory cells. The addressing and control circuitry receives an address enable signal to initiate an access of the array whereby an address is received, decoded, and corresponding data retrieved or stored. Edge detection circuitry receives a memory clock and provides the address enable signal upon each rising edge and each falling edge of the memory clock to perform two memory operations in a single cycle of the memory clock. A memory operation includes addressing the memory and storing data in the memory or retrieving and latching data from the memory. In another form a double-rate dual port memory permits two independent read/write memory accesses in a single memory cycle.

    摘要翻译： 双速率存储器具有以行和列排列的单个字线存储单元阵列。 单个字线存储单元通过第一端口提供和存储数据。 寻址和控制电路耦合到单个字线存储单元的阵列。 寻址和控制电路接收地址使能信号以启动阵列的访问，由此接收，解码地址并检索或存储对应的数据。 边缘检测电路接收存储器时钟，并在存储器时钟的每个上升沿和每个下降沿提供地址使能信号，以在存储器时钟的单个周期中执行两个存储器操作。 存储器操作包括寻址存储器并将数据存储在存储器中或从存储器检索和锁存数据。 在另一种形式中，双速率双端口存储器允许在单个存储器周期中进行两个独立的读/写存储器存取。

    Output buffer
    22.
    发明授权
    Output buffer 有权
    输出缓冲区

    公开(公告)号：US06169420A

    公开(公告)日：2001-01-02

    申请号：US09131515

    申请日：1998-08-10

    申请人： John Deane Coddington ,  Perry H. Pelley, III

    发明人： John Deane Coddington ,  Perry H. Pelley, III

    IPC分类号： H03K190175

    CPC分类号： H03K19/00315

    摘要： An output buffer (200) having a protection circuit (228, 230, 232) which adjusts control of an output drive circuit (224,226) in response to external voltages on the output pin (202). When the output pin is in a tri-state condition and receives an external voltage which is outside a predetermined voltage range, the protection circuit adjusts the voltage on the control gate of a transistor (224) in the output drive circuit. The protection circuit maintains the voltage across the transistor within the tolerance of the transistor. In one embodiment, the output drive circuit has pullup (204) and pulldown (206) portions. The output buffer provides a high voltage output driver having low voltage devices.

    摘要翻译： 一种具有保护电路（228,230,232）的输出缓冲器（200），其响应于输出引脚（202）上的外部电压来调节对输出驱动电路（224,226）的控制。 当输出引脚处于三态状态并接收超出预定电压范围的外部电压时，保护电路调节输出驱动电路中的晶体管（224）的控制栅上的电压。 保护电路将晶体管两端的电压保持在晶体管的容限内。 在一个实施例中，输出驱动电路具有上拉（204）和下拉（206）部分。 输出缓冲器提供具有低电压器件的高电压输出驱动器。

    BICMOS latch circuit for latching differential signals
    23.
    发明授权
    BICMOS latch circuit for latching differential signals 失效
    用于锁存差分信号的BICMOS锁存电路

    公开(公告)号：US5760626A

    公开(公告)日：1998-06-02

    申请号：US626703

    申请日：1996-04-01

    申请人： Perry H. Pelley, III

    发明人： Perry H. Pelley, III

    IPC分类号： H03K3/021 ,  H03K3/287 ,  H03K3/12

    CPC分类号： H03K3/287 ,  H03K3/021

    摘要： A data value is passed from a bus (50) to a receiver (40) without a propagation delay. A data latch (10) stores the data value while the data value is being generated by the bus (50). The data latch (10) then holds the data value and provides the data value to the receiver (40) after the data value is no longer present on the bus (50). The data latch (10) has a data storage circuit (11), a diode clamping circuit (12), and a current sourcing circuit (13). The data value is stored by the data storage circuit (11) by a feed-back loop circuit.

    摘要翻译： 数据值从总线（50）传递到接收器（40）而没有传播延迟。 数据锁存器（10）在总线（50）正在生成数据值的同时存储数据值。 数据锁存器（10）然后保存数据值，并且在数据值不再存在于总线（50）上之后将数据值提供给接收器（40）。 数据锁存器（10）具有数据存储电路（11），二极管钳位电路（12）和电流源电路（13）。 数据值由数据存储电路（11）由反馈回路电路存储。

    Localized ATD summation for a memory
    24.
    发明授权
    Localized ATD summation for a memory 失效
    存储器的本地ATD求和

    公开(公告)号：US5323360A

    公开(公告)日：1994-06-21

    申请号：US55596

    申请日：1993-05-03

    申请人： Perry H. Pelley, III

    发明人： Perry H. Pelley, III

    IPC分类号： G11C11/41 ,  G11C7/22 ,  G11C8/18 ,  G11C8/00

    CPC分类号： G11C8/18 ,  G11C7/22

    摘要： A memory (110) having sections of memory cells used ATD to generate the required timing signals, includes ATD generators (189), first summation circuits (180-183), and local summation circuits 185-187. An ATD pulse is generated by the ATD generators (189) when an address signal transitions from one logic state to another. The outputs of the ATD generators (189) are wired-OR connected to input terminals of first summation circuits (180-183). A first summation signal is provided by the first summation circuits (180-183) to each of the local summation circuits (185-187). The local summation circuits (185-187) are positioned in the vicinity of the areas where the timing signals are used. Localized generation of the ATD signals prevents the timing signals for being excessively skewed from each other in different portions of the memory (110).

    摘要翻译： 具有使用ATD的存储单元部分生成所需定时信号的存储器（110）包括ATD发生器（189），第一求和电路（180-183）和局部求和电路185-187。 当地址信号从一个逻辑状态转变到另一个逻辑状态时，由ATD发生器（189）产生ATD脉冲。 ATD发生器（189）的输出被或线连接到第一求和电路（180-183）的输入端。 第一求和信号由第一求和电路（180-183）提供给每个局部求和电路（185-187）。 局部求和电路（185-187）位于使用定时信号的区域附近。 ATD信号的本地产生防止定时信号在存储器（110）的不同部分中彼此过度偏斜。

    Technique restore for a dynamic random access memory
    26.
    发明授权
    Technique restore for a dynamic random access memory 失效
    技术恢复动态随机存取存储器

    公开(公告)号：US4710902A

    公开(公告)日：1987-12-01

    申请号：US784449

    申请日：1985-10-04

    申请人： Perry H. Pelley, III ,  Bruce L. Morton

    发明人： Perry H. Pelley, III ,  Bruce L. Morton

    IPC分类号： G11C11/401 ,  G11C11/406 ,  G11C11/409 ,  G11C11/4091 ,  G11C7/00 ,  G11C11/24 ,  G11C11/34

    CPC分类号： G11C11/406 ,  G11C11/4091

    摘要： Memory cells in a dynamic random access memory are coupled to bit lines which are coupled to sense amplifiers. Memory cells are enabled by an enabled word line which causes the memory cells to output data onto the bit lines to which they are coupled. A selected bit line is coupled to a data line while the sense amplifier is amplifying the signal provided by the memory cell. The effect of coupling the bit line to the data line is to hinder the refresh of the selected memory cell because the bit line does not reach full power supply voltage due to the loading by the data line. Full refresh is obtained by keeping the word line enabled for a predetermined time following the bit line being decoupled from the data line so the sense amplifier can bring the bit line to full power supply potential.

    摘要翻译： 动态随机存取存储器中的存储器单元耦合到耦合到读出放大器的位线。 存储器单元由使能的字线使能，这使得存储器单元将数据输出到与它们耦合到的位线上。 选择的位线耦合到数据线，同时读出放大器放大由存储单元提供的信号。 将位线耦合到数据线的效果是阻碍所选择的存储器单元的刷新，因为位线由于数据线的加载而未达到全部电源电压。 通过在字线与数据线分离之后使字线保持预定时间，从而获得完全刷新，因此读出放大器可将位线带到全电源电位。

    Redundant column substitution architecture with improved column access time
    27.
    发明授权
    Redundant column substitution architecture with improved column access time 失效
    冗余列替代架构，具有改进的列访问时间

    公开(公告)号：US4691300A

    公开(公告)日：1987-09-01

    申请号：US811856

    申请日：1985-12-20

    申请人： Perry H. Pelley, III ,  Alan Lewandowski

    发明人： Perry H. Pelley, III ,  Alan Lewandowski

    IPC分类号： G11C29/00 ,  G11C13/00

    CPC分类号： G11C29/846

    摘要： An apparatus and method for redundant column substitution in a memory device with column redundancy. Rather than inhibiting normal column decoding and selecting in response to a defective column address, the present invention proceeds in parallel with normal column access and redundant column access. The I/O multiplexer receives both the normal and redundant data and, in response to an input from the redundant column decoder, selects the redundant data. Column access time is improved in the case of substituted redundant columns due to the lack of inhibiting the normal column select process. Redundant columns are located physically close to the I/O multiplexer to provide for shorter I/O lines and further improved access time for the redundant columns. Floating normal bit lines are avoided in this scheme since normal column selection is not inhibited.

    摘要翻译： 具有列冗余的存储器件中的冗余列替换的装置和方法。 本发明与正常的列访问和冗余列访问并行进行，而不是抑制正常列解码和响应于缺陷列地址的选择。 I / O多路复用器接收正常和冗余数据，并且响应于冗余列解码器的输入选择冗余数据。 在取代冗余列的情况下，由于缺乏禁止正常的列选择过程，列存取时间得到改善。 冗余列位于物理上靠近I / O多路复用器，以提供更短的I / O线，并进一步改善冗余列的访问时间。 在该方案中避免了浮动正常位线，因为不禁止正常的列选择。

    Embedded substrate interconnect for underside contact to source and drain regions
    29.
    发明授权
    Embedded substrate interconnect for underside contact to source and drain regions 有权
    用于下侧接触源极和漏极区域的嵌入式衬底互连

    公开(公告)号：US07345344B2

    公开(公告)日：2008-03-18

    申请号：US11356229

    申请日：2006-02-16

    申请人： Perry H. Pelley, III ,  Troy L. Cooper ,  Michael A. Mendicino

    发明人： Perry H. Pelley, III ,  Troy L. Cooper ,  Michael A. Mendicino

    IPC分类号： H01L27/01

    CPC分类号： H01L29/41733 ,  H01L21/84 ,  H01L27/12

    摘要： A semiconductor topography (10) is provided which includes a semiconductor-on-insulator (SOI) substrate having a conductive line (16) arranged within an insulating layer (22) of the SOI substrate. A method for forming an SOI substrate with such a configuration includes forming a first conductive line (16) within an insulating layer (22) arranged above a wafer substrate (12) and forming a silicon layer (24) upon surfaces of the first conductive line and the insulating layer. A further method is provided which includes the formation of a transistor gate (28) upon an SOI substrate having a conductive line (16) embedded therein and implanting dopants within the semiconductor topography to form source and drain regions (30) within an upper semiconductor layer (24) of the SOI substrate such that an underside of one of the source and drain regions is in contact with the conductive line.

    摘要翻译： 提供一种半导体图形（10），其包括绝缘体上半导体（SOI）基板，其具有布置在SOI衬底的绝缘层（22）内的导线（16）。 一种用于形成具有这种结构的SOI衬底的方法包括在布置在晶片衬底（12）上方的绝缘层（22）内形成第一导电线（16），并在第一导线的表面上形成硅层（24） 和绝缘层。 提供了一种另外的方法，其包括在SOI衬底上形成晶体管栅极（28），该SOI衬底具有嵌入其中的导线（16），并且在半导体拓扑图内注入掺杂剂以在上半导体层内形成源区和漏区（30） （24），使得源极和漏极区域之一的下侧与导电线接触。