公开(公告)号：US11657238B2

公开(公告)日：2023-05-23

申请号：US16779491

申请日：2020-01-31

Applicant: QUALCOMM Incorporated

Inventor： Ankit Srivastava ,  Seyed Arash Mirhaj ,  Guoqing Miao ,  Seyfi Bazarjani

IPC: G06G7/12 ,  G11C11/412 ,  G11C11/419 ,  G06G7/16

CPC classification number: G06G7/12 ,  G11C11/412 ,  G11C11/419 ,  G06G7/16

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverter for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line.

公开(公告)号：US11538509B2

公开(公告)日：2022-12-27

申请号：US17204649

申请日：2021-03-17

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash Mirhaj ,  Ankit Srivastava ,  Sameer Wadhwa ,  Ren Li ,  Suren Mohan

IPC: G11C11/419 ,  G11C7/12 ,  G11C7/10 ,  G11C7/18

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate formed by a pair of switches for multiplying the stored bit with an input vector bit. A controller controls the pair of switches responsive to a sign bit during a computation phase of operation and controls the pair of switches responsive to a magnitude bit during an execution phase of operation.

公开(公告)号：US11024358B1

公开(公告)日：2021-06-01

申请号：US16885148

申请日：2020-05-27

Applicant: QUALCOMM Incorporated

Inventor： Ankit Srivastava

IPC: G11C11/24 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/408

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverter for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a positive capacitor. A first plate of the positive capacitor connects to a positive read bit line. An inverter inverts a voltage of the second plate of the positive capacitor to drive a first plate of a negative capacitor having a second plate connected to a negative read bit line.

公开(公告)号：US20180188847A1

公开(公告)日：2018-07-05

申请号：US15470731

申请日：2017-03-27

Applicant: QUALCOMM Incorporated

Inventor： Ankit Srivastava ,  Mohamed Imtiaz Ahmed ,  Dustin Tarl Dunwell ,  William Martin Snelgrove ,  Ayaz Hasan ,  Matthew David James

IPC: G06F3/044 ,  G06F3/041

CPC classification number: G06F3/044 ,  G06F3/041 ,  G06F3/0412 ,  G06F3/0416 ,  G06F2203/04104

Abstract: In some aspects of the present disclosure, a method for touch-panel processing is provided. The method includes receiving a plurality of sensor signals from a touch panel, wherein each one of the plurality of sensor signals corresponds to a respective one of a plurality of channels of the touch panel. The method also includes, for each one of the received sensor signals, converting the received sensor signal into one or more respective digital values. The method further includes, for each one of the received sensor signals, performing digital processing on the one or more respective digital values using a respective one of a plurality of processing engines to generate one or more respective processed digital values. The method further includes performing additional processing on the processed digital values.

公开(公告)号：US20180188846A1

公开(公告)日：2018-07-05

申请号：US15470704

申请日：2017-03-27

Applicant: QUALCOMM Incorporated

Inventor： Ankit Srivastava ,  Mohamed Imtiaz Ahmed ,  Dustin Tarl Dunwell ,  William Martin Snelgrove ,  Ayaz Hasan ,  Matthew David James

IPC: G06F3/044 ,  G06F3/041

CPC classification number: G06F3/044 ,  G06F3/0412 ,  G06F3/0416

Abstract: In some aspects of the present disclosure, a touch-panel interface includes a plurality of receivers, wherein each of the receivers is coupled to one or more receive lines of a touch panel, and each of the receivers includes a switch capacitor network and an amplifier. The touch-panel interface also includes controller configured to control switches in the switch capacitor network of each of one or more of the receivers to operate each of the one or more of the receivers in one of a plurality of different receiver modes.

公开(公告)号：US09461595B2

公开(公告)日：2016-10-04

申请号：US14210905

申请日：2014-03-14

Applicant: QUALCOMM Incorporated

Inventor： Jingxue Lu ,  Matthew David Sienko ,  Ankit Srivastava ,  Manu Mishra

IPC: H03F1/02 ,  H03F3/185 ,  H03F3/45 ,  H03F1/30 ,  H03F3/183 ,  H03F3/217

CPC classification number: H03F1/0233 ,  H03F1/30 ,  H03F3/183 ,  H03F3/185 ,  H03F3/2173 ,  H03F3/45076 ,  H03F2200/03

Abstract: An apparatus includes voltage-to-current conversion circuitry comprising a first voltage-to-current converter and a second voltage-to-current converter. The apparatus also includes a capacitor coupled to the first voltage-to-current converter and to the second voltage-to-current converter.

Abstract translation: 一种装置包括包括第一电压 - 电流转换器和第二电压 - 电流转换器的电压 - 电流转换电路。 该装置还包括耦合到第一电压 - 电流转换器和第二电压 - 电流转换器的电容器。

公开(公告)号：US09054520B2

公开(公告)日：2015-06-09

申请号：US13745949

申请日：2013-01-21

Applicant: QUALCOMM Incorporated

Inventor： Eugene R. Worley ,  Mingliang Wang ,  Ankit Srivastava ,  Song S. Shi

IPC: H02H9/00 ,  H02H9/04

CPC classification number: H02H9/046

Abstract: In a particular embodiment, an apparatus includes an electrostatic discharge (ESD) clamping transistor coupled to a ground terminal of a device. The apparatus further includes a switch coupled between a body terminal of the ESD clamping transistor and the around terminal.

Abstract translation: 在特定实施例中，一种装置包括耦合到装置的接地端子的静电放电（ESD）钳位晶体管。 该装置还包括耦合在ESD钳位晶体管的主体端子和周围端子之间的开关。

公开(公告)号：US09014381B2

公开(公告)日：2015-04-21

申请号：US13723170

申请日：2012-12-20

Applicant: QUALCOMM Incorporated

Inventor： Xiaohong Quan ,  Peter J. Shah ,  Ankit Srivastava ,  Guoqing Miao

IPC: H03G11/00 ,  H04R3/00 ,  H04R29/00

CPC classification number: H04R3/007 ,  H04R29/001

Abstract: Techniques for sensing the resistance of a load. In an aspect, a sense resistor is provided in series with the load. Each terminal of the sense resistor is alternately coupled via switches to a sense amplifier. A second input of the sense resistor is coupled to a terminal of the load. The voltage drop across the load and the voltage drop across the load plus sense resistor are alternatively measured. These voltage drops may be digitized and used to compute a resistance of the load using, e.g., a digital processor.

Abstract translation: 用于感测负载电阻的技术。 在一方面，与负载串联提供感测电阻器。 检测电阻器的每个端子通过开关交替耦合到读出放大器。 检测电阻的第二输入耦合到负载的端子。 交替地测量负载上的电压降和负载+检测电阻两端的电压降。 这些电压降可以被数字化并且用于使用例如数字处理器来计算负载的电阻。

公开(公告)号：US20140029611A1

公开(公告)日：2014-01-30

申请号：US13841355

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Xuhao Huang ,  Ankit Srivastava ,  Xiaohong Quan ,  Seyfollah S. Bazarjani

IPC: H04L12/947

CPC classification number: H04L49/25 ,  H04L12/40006 ,  H04L12/4035 ,  H04L25/0272

Abstract: An apparatus for sharing a serial communication port between a plurality of communication channels is described. The apparatus comprises a transceiver that manages communications over the serial communication port. The apparatus also includes a multiplexer coupled to the transceiver, wherein the multiplexer multiplexes the plurality of communication channels. The apparatus also includes identification information circuitry coupled to the multiplexer, wherein the identification information circuitry adds identification information to data from the plurality of communication channels that enables the plurality of communication channels to share the serial communication port. The serial communications port and the multiplexer permit communication between integrated circuits that meet at least one latency metric for the plurality of communication channels when the plurality of communication channels are active.

Abstract translation: 描述了用于在多个通信信道之间共享串行通信端口的装置。 该装置包括管理串行通信端口上的通信的收发器。 该设备还包括耦合到收发器的多路复用器，其中复用器复用多个通信信道。 该装置还包括耦合到多路复用器的识别信息电路，其中识别信息电路将识别信息添加到来自多个通信信道的数据，使多个通信信道能够共享串行通信端口。 串行通信端口和多路复用器允许在多个通信信道有效时满足多个通信信道的至少一个等待时间度量的集成电路之间的通信。

公开(公告)号：US11631455B2

公开(公告)日：2023-04-18

申请号：US17152564

申请日：2021-01-19

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash Mirhaj ,  Xiaonan Chen ,  Ankit Srivastava ,  Sameer Wadhwa ,  Zhongze Wang

IPC: G11C11/419 ,  G06F7/544

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line. A write driver controls a power supply voltage to the cross-coupled inverters, the first switch, and the second switch to capacitively write the stored bit to the pair of cross-coupled inverters.