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    LOW LATENCY SYNCHRONIZATION SCHEME FOR MESOCHRONOUS DDR SYSTEM
    3.
    发明申请
    LOW LATENCY SYNCHRONIZATION SCHEME FOR MESOCHRONOUS DDR SYSTEM 有权
    用于MESOCHRONOUS DDR系统的低延迟同步方案

    公开(公告)号：US20140347941A1

    公开(公告)日：2014-11-27

    申请号：US13902705

    申请日：2013-05-24

    Applicant: QUALCOMM Incorporated

    Inventor： Edwin Jose ,  Michael Drop ,  Xuhao Huang ,  Raghu Sankuratri ,  Deepti Sriramagiri ,  Marzio Pedrali-Noy

    IPC: G11C7/22

    CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4093 ,  G11C2207/2254 ,  H03L7/093 ,  Y02D10/14

    Abstract: In one embodiment, a memory interface comprises a cleanup phase-locked loop (PLL) configured to receive a reference clock signal, and to generate a clean clock signal based on the reference clock signal. The memory interface also comprises a synchronization circuit configured to receive data, a data clock signal, and the clean clock signal, wherein the synchronization circuit is further configured to sample the data using the data clock signal, and to synchronize the sampled data with the clean clock signal.

    Abstract translation: 在一个实施例中，存储器接口包括被配置为接收参考时钟信号的清理锁相环（PLL），并且基于参考时钟信号产生干净的时钟信号。 存储器接口还包括被配置为接收数据，数据时钟信号和清洁时钟信号的同步电路，其中同步电路还被配置为使用数据时钟信号对数据进行采样，并使采样数据与干净的 时钟信号。

    SYSTEMS AND METHODS FOR SHARING A SERIAL COMMUNICATION PORT BETWEEN A PLURALITY OF COMMUNICATION CHANNELS
    4.
    发明申请
    SYSTEMS AND METHODS FOR SHARING A SERIAL COMMUNICATION PORT BETWEEN A PLURALITY OF COMMUNICATION CHANNELS 有权
    在多个通信信道之间共享串行通信端口的系统和方法

    公开(公告)号：US20140029611A1

    公开(公告)日：2014-01-30

    申请号：US13841355

    申请日：2013-03-15

    Applicant: QUALCOMM INCORPORATED

    Inventor： Xuhao Huang ,  Ankit Srivastava ,  Xiaohong Quan ,  Seyfollah S. Bazarjani

    IPC: H04L12/947

    CPC classification number: H04L49/25 ,  H04L12/40006 ,  H04L12/4035 ,  H04L25/0272

    Abstract: An apparatus for sharing a serial communication port between a plurality of communication channels is described. The apparatus comprises a transceiver that manages communications over the serial communication port. The apparatus also includes a multiplexer coupled to the transceiver, wherein the multiplexer multiplexes the plurality of communication channels. The apparatus also includes identification information circuitry coupled to the multiplexer, wherein the identification information circuitry adds identification information to data from the plurality of communication channels that enables the plurality of communication channels to share the serial communication port. The serial communications port and the multiplexer permit communication between integrated circuits that meet at least one latency metric for the plurality of communication channels when the plurality of communication channels are active.

    Abstract translation: 描述了用于在多个通信信道之间共享串行通信端口的装置。 该装置包括管理串行通信端口上的通信的收发器。 该设备还包括耦合到收发器的多路复用器，其中复用器复用多个通信信道。 该装置还包括耦合到多路复用器的识别信息电路，其中识别信息电路将识别信息添加到来自多个通信信道的数据，使多个通信信道能够共享串行通信端口。 串行通信端口和多路复用器允许在多个通信信道有效时满足多个通信信道的至少一个等待时间度量的集成电路之间的通信。

    Method of generating precise and PVT-stable time delay or frequency using CMOS circuits
    5.
    发明授权
    Method of generating precise and PVT-stable time delay or frequency using CMOS circuits 有权

    公开(公告)号：US11196410B2

    公开(公告)日：2021-12-07

    申请号：US17022608

    申请日：2020-09-16

    Applicant: QUALCOMM Incorporated

    Inventor： Zhengzheng Wu ,  Xu Zhang ,  Xuhao Huang

    IPC: H03K5/134 ,  H03K3/03 ,  H03K5/00

    Abstract: A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.

    Low-power temperature-insensitive current bias circuit
    6.
    发明授权
    Low-power temperature-insensitive current bias circuit 有权

    公开(公告)号：US10185337B1

    公开(公告)日：2019-01-22

    申请号：US15945568

    申请日：2018-04-04

    Applicant: QUALCOMM Incorporated

    Inventor： Sungmin Ock ,  Wenjing Yin ,  Xuhao Huang

    IPC: G05F1/46 ,  H03K17/687

    Abstract: A bias current circuit is provided with a bias circuit that generates a bias voltage to control the resistance of an active resistor transistor. The bias circuit is configured to generate the bias voltage to be greater than one-half of a power supply voltage for the current bias circuit and to have a negative temperature dependency to reduce the temperature sensitivity of the bias current circuit.

    Method of generating precise and PVT-stable time delay or frequency using CMOS circuits
    8.
    发明授权
    Method of generating precise and PVT-stable time delay or frequency using CMOS circuits 有权

    公开(公告)号：US10812056B1

    公开(公告)日：2020-10-20

    申请号：US16722572

    申请日：2019-12-20

    Applicant: QUALCOMM Incorporated

    Inventor： Zhengzheng Wu ,  Xu Zhang ,  Xuhao Huang

    IPC: H03K5/134 ,  H03K3/03 ,  H03K5/00

    Abstract: A method of generating precise and PVT-stable time delay or frequency using CMOS circuits is disclosed. In some implementations, the method includes providing a reference voltage using a resistive module at a positive input terminal of an operational amplifier, coupling gates of a pair of p-type metal oxide semiconductor (pMOS) transistors and a compensation capacitor to an output terminal of the operational amplifier to generate a first bias signal, and coupling a pair of n-type metal oxide semiconductor (nMOS) transistors to a negative terminal of the operational amplifier to generate a second bias signal at the negative terminal, wherein the pair of nMOS transistors is substantially the same as a pair of nMOS transistors in the CMOS delay circuit.

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