公开(公告)号：US10114585B2

公开(公告)日：2018-10-30

申请号：US15448203

申请日：2017-03-02

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Hao Chu ,  Subrato Kumar De ,  Dexter Tamio Chun ,  Bohuslav Rychlik ,  Richard Alan Stewart

IPC: G06F3/06 ,  G06F13/16

Abstract: Various aspects are described herein. In some aspects, the present disclosure provides a method of communicating data between an electronic unit of a system-on-chip (SoC) and a dynamic random access memory (DRAM). The method includes initiating a memory transaction corresponding to first data. The method includes determining a non-unique first signature and a unique second signature associated with the first data based on content of the first data. The method includes determining if the non-unique first signature is stored in at least one of a local buffer on the SoC separate from the DRAM or the DRAM. The method includes determining if the unique second signature is stored in at least one of the local buffer or the DRAM based on determining the non-unique first signature is stored. The method includes eliminating the memory transaction with respect to the DRAM based on determining the unique second signature is stored.

公开(公告)号：US20180114553A1

公开(公告)日：2018-04-26

申请号：US15849463

申请日：2017-12-20

Applicant: QUALCOMM Incorporated

Inventor： David Ian West ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  Vaishnav Srinivas

IPC: G11C7/10 ,  G06F11/10 ,  G06F12/00 ,  G11C11/4076 ,  G11C11/406

CPC classification number: G11C7/1063 ,  G06F11/1004 ,  G06F11/1048 ,  G06F12/00 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076

Abstract: Dynamic random access memory (DRAM) backchannel communication systems and methods are disclosed. In one aspect, a backchannel communication system allows a DRAM to communicate error correction information and refresh alert information to a System on a Chip (SoC), applications processor (AP), or other memory controller.

公开(公告)号：US09881656B2

公开(公告)日：2018-01-30

申请号：US14591056

申请日：2015-01-07

Applicant: QUALCOMM Incorporated

Inventor： David Ian West ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  Vaishnav Srinivas

IPC: G11C7/10 ,  G06F11/10 ,  G11C11/406 ,  G06F12/00 ,  G11C11/4076

CPC classification number: G11C7/1063 ,  G06F11/1004 ,  G06F11/1048 ,  G06F12/00 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076

Abstract: Dynamic random access memory (DRAM) backchannel communication systems and methods are disclosed. In one aspect, a backchannel communication system allows a DRAM to communicate error correction information and refresh alert information to a System on a Chip (SoC), applications processor (AP), or other memory controller.

公开(公告)号：US09640242B1

公开(公告)日：2017-05-02

申请号：US14956565

申请日：2015-12-02

Applicant: QUALCOMM INCORPORATED

Inventor： Haw-Jing Lo ,  Dexter Tamio Chun

IPC: G11C11/34 ,  G11C11/406 ,  G11C11/4074

CPC classification number: G11C11/40626 ,  G06F1/3225 ,  G06F1/3275 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4074 ,  Y02D10/13 ,  Y02D10/14

Abstract: Various embodiments of methods and systems for temperature compensated memory refresh (“TCMR”) of a dynamic random access memory (“DRAM”) component are disclosed. Embodiments of the solution leverage a memory refresh module located within a memory subsystem to apply a refresh power supply received from a source on the SoC. Advantageously, even though the refresh power supply is received from a source on the SoC according to a certain delivery rate that may not be optimal for each and every bank in the DRAM component, embodiments of the solution are able to apply an effective refresh power supply rate to each bank according to its optimal cycle.

公开(公告)号：US09472261B1

公开(公告)日：2016-10-18

申请号：US14690204

申请日：2015-04-17

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Jung Pill Kim ,  Yanru Li

IPC: G11C5/00 ,  G11C7/00 ,  G11C29/00 ,  G11C7/04 ,  G11C11/406 ,  G11C11/4096 ,  G11C29/42 ,  G11C29/36

CPC classification number: G11C11/40626 ,  G11C7/1006 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C29/36 ,  G11C29/42 ,  G11C29/50016 ,  G11C2207/2245 ,  G11C2211/4062

Abstract: A system and method of refreshing dynamic random access memory (DRAM) are disclosed. A device includes a DRAM, a bus, and a system-on-chip (SOC) coupled via the bus to the DRAM. The SOC is configured to refresh the DRAM at a particular refresh rate based on a temperature of the DRAM and based on calibration data determined based on one or more calibration tests performed while the SOC is coupled to the DRAM.

Abstract translation: 公开了一种刷新动态随机存取存储器（DRAM）的系统和方法。 一种器件包括通过总线耦合到DRAM的DRAM，总线和片上系统（SOC）。 SOC被配置为基于DRAM的温度以基于在SOC耦合到DRAM时执行的一个或多个校准测试确定的校准数据以特定刷新速率刷新DRAM。

公开(公告)号：US09396109B2

公开(公告)日：2016-07-19

申请号：US14142573

申请日：2013-12-27

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Haw-Jing Lo ,  Michael Drop

IPC: G06F12/06 ,  G06F1/32 ,  G06F13/16

CPC classification number: G06F12/06 ,  G06F1/3225 ,  G06F1/3275 ,  G06F13/1673 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: Aspects include computing devices, systems, and methods for reorganizing the storage of data in memory to energize less than all of the memory devices of a memory module for read or write transactions. The memory devices may be connected to individual select lines such that a re-order logic may determine the memory devices to energize for a transaction according to a re-ordered memory map. The re-order logic may re-order memory addresses such that memory address provided by a processor for a transaction are converted to the re-ordered memory address according to the re-ordered memory map without the processor having to change its memory address scheme. The re-ordered memory map may provide for reduced energy consumption by the memory devices, or a balance of energy consumption and performance speed for latency tolerant processes.

Abstract translation: 方面包括用于重新组织存储器中的数据存储器的计算设备，系统和方法，以激励小于用于读取或写入事务的存储器模块的所有存储器设备。 存储器件可以连接到单独的选择线，使得重新排序逻辑可以根据重新排序的存储器映射来确定存储器件激活事务。 重新排序逻辑可以重新排序存储器地址，使得由处理器为交易提供的存储器地址根据重新排序的存储器映射被转换为重新排序的存储器地址，而处理器不必改变其存储器地址方案。 重新排序的存储器映射可以提供由存储器件减少的能量消耗，或等待容忍过程的能量消耗和性能速度的平衡。

公开(公告)号：US11295803B2

公开(公告)日：2022-04-05

申请号：US16945303

申请日：2020-07-31

Applicant: QUALCOMM Incorporated ,  Candace Sachi Chun

Inventor： Jungwon Suh ,  Michael Hawjing Lo ,  Dexter Tamio Chun ,  Xavier Loic Leloup ,  Laurent Rene Moll

IPC: G11C5/14 ,  G11C11/4074 ,  G11C11/409

Abstract: Methods and apparatuses for to memories using dynamic voltage scaling are presented. The apparatus includes memory configured to communicate with a host. The memory includes a peripheral portion and a memory array. The memory is further configured to receive, from at least one power management circuit, a first supply voltage and a second supply voltage. The memory further includes a switch circuit. The switch circuit is configured to selectively provide the first supply voltage and the second supply voltage to the peripheral portion. The first supply voltage is static and has a first voltage range. The second supply voltage has a low second voltage range and a high second voltage range.

公开(公告)号：US20210358559A1

公开(公告)日：2021-11-18

申请号：US17245981

申请日：2021-04-30

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Tamio Chun ,  Anand Srinivasan ,  Olivier Alavoine ,  Laurent Rene Moll

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  G11C7/10

Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.

公开(公告)号：US10853163B2

公开(公告)日：2020-12-01

申请号：US15942372

申请日：2018-03-30

Applicant: QUALCOMM Incorporated

Inventor： Alain Artieri ,  Deepti Vijayalakshmi Sriramagiri ,  Dexter Tamio Chun ,  Jungwon Suh

IPC: G06F11/10 ,  G06F3/06 ,  H04L1/00 ,  H03M13/19 ,  G11C29/52 ,  G11C29/02 ,  G11C29/04

Abstract: Disclosed are techniques for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message. In an aspect, a method includes initializing a matrix M to store selected three-bit codes, selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M, comparing the first three-bit code with each of a plurality of error syndromes, and calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes, new error syndromes and storing the new error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M.

公开(公告)号：US10387242B2

公开(公告)日：2019-08-20

申请号：US15682533

申请日：2017-08-21

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Alain Artieri ,  Dexter Tamio Chun ,  Deepti Vijayalakshmi Sriramagiri

IPC: G11C29/00 ,  G06F11/10 ,  G06F3/06

Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.