公开(公告)号：US20210091017A1

公开(公告)日：2021-03-25

申请号：US16870642

申请日：2020-05-08

Applicant: QUALCOMM Incorporated

Inventor： Jaehyun YEON ,  Suhyung HWANG ,  Chin-Kwan KIM ,  Rajneesh KUMAR ,  Darryl Sheldon JESSIE

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/52 ,  H01Q1/22 ,  H01Q5/307 ,  H01Q9/16

Abstract: A package comprising a substrate, a first antenna device, and an integrated device. The substrate comprising a first surface and a second surface, where the substrate comprises a plurality of interconnects. The first antenna device is coupled to the first surface of the substrate, through a first plurality of solder interconnects. The integrated device is coupled to the second surface of the substrate. The package may include an encapsulation layer located over the second surface of the substrate, where the encapsulation layer encapsulates the integrated device. The package may include a shield formed over a surface of the encapsulation layer, where the shield includes an electromagnetic interference (EMI) shield.

公开(公告)号：US20180286562A1

公开(公告)日：2018-10-04

申请号：US15476823

申请日：2017-03-31

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Chin-Kwan KIM ,  Joonsuk PARK

IPC: H01F27/28 ,  H01L49/02 ,  H01F27/29 ,  H01F38/00

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F17/04 ,  H01F27/292 ,  H01F2017/048

Abstract: Examples of this disclosure include a low profile inductor for use in any application with a multi-layer inductor pattern that allows control of optimum H values. Some examples of such an inductive device comprises a plurality of patterned metal coils arranged in a vertical stack, a plurality of conductive vias configured to couple each of the plurality of patterned metal coils together, and a magnetic material disposed between the plurality of patterned metal coils and within each of the plurality of patterned metal coils.

公开(公告)号：US20150206812A1

公开(公告)日：2015-07-23

申请号：US14263823

申请日：2014-04-28

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan KIM ,  Milind Pravin SHAH ,  Manuel ALDRETE

IPC: H01L23/053 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/3205

CPC classification number: H01L23/053 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Methods and apparatus for cavity formation in a semiconductor package substrate are provided. In one embodiment, a method for producing at least one cavity within a semiconductor package substrate includes etching the semiconductor package substrate from a surface of the semiconductor package substrate at least one intended cavity location in order to obtain at least one cavity. The method includes depositing a copper portion on a substrate in a cavity location. Next, the method includes masking the substrate while keeping the copper portion exposed. Lastly, the method includes etching the substrate to form a cavity by etching away the copper portion. The structure formed includes a cavity that extends partially through the substrate without damaging a glass fabric embedded in the substrate.

Abstract translation: 提供了半导体封装基板中的空腔形成方法和装置。 在一个实施例中，一种用于在半导体封装衬底内产生至少一个空腔的方法包括从半导体封装衬底的表面至少一个预定的腔位置蚀刻半导体封装衬底，以便获得至少一个空腔。 该方法包括在空腔位置的基板上沉积铜部分。 接下来，该方法包括在保持铜部分暴露的同时掩蔽基板。 最后，该方法包括通过蚀刻掉铜部分来蚀刻基板以形成空腔。 所形成的结构包括部分地延伸穿过基底的空腔，而不会损害嵌入在基底中的玻璃织物。