公开(公告)号：US20190156895A1

公开(公告)日：2019-05-23

申请号：US16260026

申请日：2019-01-28

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Xiao LU ,  Xiaonan CHEN ,  Zhongze WANG

IPC: G11C16/10 ,  G11C17/14 ,  H01L27/112 ,  H01L29/792 ,  G11C16/04 ,  G11C17/18 ,  G11C17/16 ,  H01L29/423

Abstract: A semiconductor device for a one-time programmable (OTP) memory according to some examples of the disclosure includes a gate, a dielectric region below the gate, a source terminal below the dielectric region and offset to one side, a drain terminal below the dielectric region and offset to an opposite side from the source terminal, a drain side charge trap in the dielectric region capable of programming the semiconductor device, and a source side charge trap in the dielectric region opposite the drain side charge trap and capable of programming the semiconductor device.

公开(公告)号：US20160133634A1

公开(公告)日：2016-05-12

申请号：US14995195

申请日：2016-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： Niladri Narayan MOJUMDER ,  Stanley Seungchul SONG ,  Zhongze WANG ,  Choh Fei YEAP

IPC: H01L27/11 ,  H01L29/423 ,  H01L27/105

CPC classification number: H01L27/1052 ,  G11C11/412 ,  H01L27/1104 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/785

Abstract: A complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cell. A CMOS SRAM cell in accordance with an aspect of the present disclosure includes a bit line and a word line. Such a CMOS SRAM memory cell further includes a CMOS memory cell having at least a first p-channel device comprising a first channel material that differs from a substrate material of the CMOS memory cell, the first channel material having an intrinsic channel mobility greater than the intrinsic channel mobility of the substrate material, the first p-channel device coupling the CMOS memory cell to the bit line and the word line.

公开(公告)号：US20160126137A1

公开(公告)日：2016-05-05

申请号：US14993065

申请日：2016-01-11

Applicant: QUALCOMM Incorporated

Inventor： John J. ZHU ,  Zhongze WANG ,  Da YANG

IPC: H01L21/768

CPC classification number: H01L21/76894 ,  G03F7/7045 ,  G03F7/70466 ,  H01L21/28123 ,  H01L21/283 ,  H01L21/31 ,  H01L21/469 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/50 ,  H01L24/27 ,  H01L24/31 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip. A method includes patterning a first portion of a feature (such as a local interconnect) and a second portion of the feature to be separated by a predetermined distance, such as a line tip to tip space or a line space. The method further includes patterning the first portion with a cut mask to form a first sub-portion (e.g., a contact) and a second sub-portion. A dimension of the first sub-portion is less than a dimension of a second predetermined distance, which may be a line length resolution of a lithographic process having a specified width resolution. A feature of a semiconductor device includes a first portion and a second portion having a dimension less than a lithographic resolution of the first portion.

Abstract translation: 特征是在半导体芯片上制造的。 这些特征小于用于制造芯片的光刻的阈值。 一种方法包括图案化特征（例如局部互连）的第一部分和要分离预定距离的特征的第二部分，例如线尖到尖端空间或线空间。 该方法还包括用切割掩模图案化第一部分以形成第一子部分（例如，接触）和第二子部分。 第一子部分的尺寸小于第二预定距离的尺寸，其可以是具有指定宽度分辨率的光刻工艺的线长分辨率。 半导体器件的特征包括具有小于第一部分的光刻分辨率的尺寸的第一部分和第二部分。

公开(公告)号：US20160043092A1

公开(公告)日：2016-02-11

申请号：US14454805

申请日：2014-08-08

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan MOJUMDER ,  Stanley Seungchul SONG ,  Zhongze WANG ,  Choh Fei YEAP

IPC: H01L27/11

CPC classification number: H01L27/1052 ,  G11C11/412 ,  H01L27/1104 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/785

Abstract: A complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cell. A CMOS SRAM cell in accordance with an aspect of the present disclosure includes a bit line and a word line. Such a CMOS SRAM memory cell further includes a CMOS memory cell having at least a first p-channel device comprising a first channel material that differs from a substrate material of the CMOS memory cell, the first channel material having an intrinsic channel mobility greater than the intrinsic channel mobility of the substrate material, the first p-channel device coupling the CMOS memory cell to the bit line and the word line.

Abstract translation: 互补金属氧化物半导体（CMOS）静态随机存取存储器（SRAM）单元。 根据本公开的一个方面的CMOS SRAM单元包括位线和字线。 这种CMOS SRAM存储单元还包括具有至少第一p沟道器件的CMOS存储器单元，该第一p沟道器件包括与CMOS存储器单元的衬底材料不同的第一沟道材料，第一沟道材料具有大于 衬底材料的固有沟道迁移率，第一p沟道器件将CMOS存储器单元耦合到位线和字线。

公开(公告)号：US20250124284A1

公开(公告)日：2025-04-17

申请号：US18989461

申请日：2024-12-20

Applicant: QUALCOMM Incorporated

Inventor： Mustafa BADAROGLU ,  Zhongze WANG

IPC: G06N3/08 ,  G06F7/50 ,  G06F7/523 ,  G06F7/544

Abstract: Methods and apparatus for performing machine learning tasks, and in particular, to a neural-network-processing architecture and circuits for improved handling of partial accumulation results in weight-stationary operations, such as operations occurring in compute-in-memory (CIM) processing elements (PEs). One example PE circuit for machine learning generally includes an accumulator circuit, a flip-flop array having an input coupled to an output of the accumulator circuit, a write register, and a first multiplexer having a first input coupled to an output of the write register, having a second input coupled to an output of the flip-flop array, and having an output coupled to a first input of the first accumulator circuit.

公开(公告)号：US20240422995A1

公开(公告)日：2024-12-19

申请号：US18336775

申请日：2023-06-16

Applicant: QUALCOMM Incorporated

Inventor： Mustafa BADAROGLU ,  Zhongze WANG ,  Woo Tag KANG ,  Periannan CHIDAMBARAM

IPC: H10B80/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A stacked system-on-chip (SoC) is described. The stacked SoC includes a first memory die comprising a dynamic random-access memory (DRAM). The stacked SoC also includes a compute logic die. The compute logic die comprises a static random-access memory (SRAM) having a first SRAM partition and a second SRAM partition. The first memory die is stacked on the compute logic die. The compute logic die includes a memory controller. The memory controller is coupled between the first SRAM partition and the second SRAM partition. Additionally, the memory controller is coupled to a DRAM bus of the first memory die.

公开(公告)号：US20210279036A1

公开(公告)日：2021-09-09

申请号：US16807562

申请日：2020-03-03

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Zhongze WANG ,  Periannan CHIDAMBARAM

IPC: G06F7/46 ,  G06N3/04 ,  G06N20/00

Abstract: Certain aspects provide methods and apparatus for binary computation. An example circuit for such computation generally includes a memory cell having at least one of a bit-line or a complementary bit-line; a computation circuit coupled to a computation input node of the circuit and the bit-line or the complementary bit-line; and an adder coupled to the computation circuit, wherein the computation circuit comprises a first n-type metal-oxide-semiconductor (NMOS) transistor coupled to the memory cell, and a first p-type metal-oxide-semiconductor (PMOS) transistor coupled to the memory cell, drains of the first NMOS and PMOS transistors being coupled to the adder, wherein a source of the first PMOS transistor is coupled to a reference potential node, and wherein a source of the first NMOS transistor is coupled to the computation input node.

公开(公告)号：US20210089865A1

公开(公告)日：2021-03-25

申请号：US16576597

申请日：2019-09-19

Applicant: QUALCOMM Incorporated

Inventor： Zhongze WANG ,  Ye LU

IPC: G06N3/04 ,  G06F7/544 ,  G06F17/15

Abstract: An apparatus includes first and second compute-in-memory (CIM) arrays. The first CIM array is configured to store weights corresponding to a filter tensor, to receive a first set of activations corresponding to a first receptive field of an input, and to process the first set of activations with the weights to generate a corresponding first tensor of output values. The second CIM array is configured to store a first copy of the weights corresponding to the filter tensor and to receive a second set of activations corresponding to a second receptive field of the input. The second CIM array is also configured to process the second set of activations with the first copy of the weights to generate a corresponding second tensor of output values. The first and second compute-in-memory arrays are configured to process the first and second receptive fields in parallel.

公开(公告)号：US20160093365A1

公开(公告)日：2016-03-31

申请号：US14499149

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Seong-Ook JUNG ,  Young Hwi YANG ,  Zhongze WANG ,  Choh Fei YEAP

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: Systems and methods relate to a seven transistor static random-access memory (7T SRAM) bit cell which includes a first inverter having a first pull-up transistor, a first pull-down transistor, and a first storage node, and a second inverter having a second pull-up transistor, a second pull-down transistor, and a second storage node. The second storage node is coupled to gates of the first pull-up transistor and the first pull-down transistor. A transmission gate is configured to selectively couple the first storage node to gates of the second pull-up transistor and the second pull-down transistor during a write operation, a standby mode, and a hold mode, and selectively decouple the first storage node from gates of the first pull-up transistor and a first pull-down transistor during a read operation. The 7T SRAM bit cell can be read or written through an access transistor coupled to the first storage node.

Abstract translation: 系统和方法涉及七晶体管静态随机存取存储器（7T SRAM）位单元，其包括具有第一上拉晶体管，第一下拉晶体管和第一存储节点的第一反相器，以及具有 第二上拉晶体管，第二下拉晶体管和第二存储节点。 第二存储节点耦合到第一上拉晶体管和第一下拉晶体管的栅极。 传输门被配置为在写入操作，待机模式和保持模式期间将第一存储节点选择性地耦合到第二上拉晶体管和第二下拉晶体管的栅极，并且选择性地将第一存储节点与 在读取操作期间第一上拉晶体管的栅极和第一下拉晶体管。 可以通过耦合到第一存储节点的存取晶体管来读取或写入7T SRAM位单元。

公开(公告)号：US20150333131A1

公开(公告)日：2015-11-19

申请号：US14281710

申请日：2014-05-19

Applicant: QUALCOMM Incorporated

Inventor： Niladri MOJUMDER ,  Stanley Seungchul SONG ,  Zhongze WANG ,  Choh Fei YEAP

IPC: H01L29/40 ,  H01L29/161 ,  H01L27/11

CPC classification number: H01L29/401 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/161

Abstract: Methods and apparatus directed toward a high density static random access memory (SRAM) array having advanced metal patterning are provided. In an example, provided is a method for fabricating an SRAM. The method includes forming, using a self-aligning double patterning (SADP) technique, a plurality of substantially parallel first metal lines oriented in a first direction in a first layer. The method also includes etching the substantially parallel first metal lines, using a cut mask, in a second direction substantially perpendicular to the first direction, to separate the substantially parallel first metal lines into a plurality of islands having first respective sides that are aligned in the first direction and second respective sides that are aligned the second direction. The method also includes forming, in a second layer, a plurality of second metal lines oriented in the first direction.

Abstract translation: 提供了针对具有高级金属图案化的高密度静态随机存取存储器（SRAM）阵列的方法和装置。 在一个示例中，提供了一种用于制造SRAM的方法。 该方法包括使用自对准双图案化（SADP）技术形成在第一层中沿第一方向定向的多个基本平行的第一金属线。 该方法还包括在基本上垂直于第一方向的第二方向上使用切割掩模蚀刻基本平行的第一金属线，以将基本上平行的第一金属线分离成多个岛，该岛具有在第 第一方向和第二相对侧对准第二方向。 该方法还包括在第二层中形成沿第一方向定向的多个第二金属线。