公开(公告)号：US20160211216A1

公开(公告)日：2016-07-21

申请号：US14819159

申请日：2015-08-05

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao Xu ,  Junjing BAO ,  John Jianhong ZHU ,  Stanley Seungchul SONG ,  Niladri Narayan MOJUMDER ,  Choh Fei YEAP

IPC: H01L23/532 ,  G05B19/418 ,  H01L21/768 ,  B29C67/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/53223 ,  B29C64/386 ,  B33Y50/02 ,  G05B19/418 ,  G05B2219/45031 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76871 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53219 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes a first metal layer including aluminum. The integrated circuit device includes a second metal layer including an interconnect structure. The interconnect structure includes a layer of first material including aluminum. The integrated circuit device includes an inter-diffusion layer that includes aluminum. The inter-diffusion layer is proximate to the first metal layer and proximate to the layer of first material including aluminum. The integrated circuit device includes a self-forming barrier layer that includes aluminum. The self-forming barrier layer is proximate to a dielectric layer and proximate to the layer of first material including aluminum.

Abstract translation: 集成电路器件包括包括铝的第一金属层。 集成电路器件包括具有互连结构的第二金属层。 互连结构包括一层包括铝的第一材料。 集成电路器件包括包括铝的互扩散层。 互扩散层靠近第一金属层并且靠近包括铝的第一材料层。 集成电路器件包括包含铝的自形成阻挡层。 自形成阻挡层靠近电介质层并且靠近包括铝的第一材料层。

公开(公告)号：US20150115473A1

公开(公告)日：2015-04-30

申请号：US14064944

申请日：2013-10-28

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Choh Fei YEAP ,  Zhongze WANG ,  Niladri Narayan MOJUMDER

IPC: H01L23/00 ,  H01L23/528

CPC classification number: H01L24/29 ,  H01L21/76251 ,  H01L21/8221 ,  H01L21/8258 ,  H01L23/528 ,  H01L24/83 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/267 ,  H01L2224/83948 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/00

Abstract: Methods for integrating heterogeneous channel material into a semiconductor device, and semiconductor devices that integrate heterogeneous channel material. A method for fabricating a semiconductor device includes processing a first substrate of a first material at a first thermal budget to fabricate a p-type device. The method further includes coupling a second substrate of a second material to the first substrate. The method also includes processing the second substrate to fabricate an n-type device at a second thermal budget that is less than the first thermal budget. The p-type device and the n-type device may cooperate to form a complementary device.

Abstract translation: 将异质沟道材料集成到半导体器件中的方法以及集成异构沟道材料的半导体器件。 一种制造半导体器件的方法包括以第一热预算处理第一材料的第一衬底以制造p型器件。 该方法还包括将第二材料的第二衬底耦合到第一衬底。 该方法还包括处理第二基板以在小于第一热预算的第二热预算下制造n型装置。 p型设备和n型设备可以协作以形成互补设备。

公开(公告)号：US20150325514A1

公开(公告)日：2015-11-12

申请号：US14274378

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan MOJUMDER ,  Zhongze WANG ,  Stanley Seungchul SONG ,  Choh Fei YEAP

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/11

CPC classification number: H01L27/1104 ,  H01L27/0207

Abstract: A static random access memory (SRAM) cell includes a first conductive layer including a wordline landing pad extending into a neighboring memory cell in an adjacent row of a memory array. The wordline landing pad in the first conductive layer is electrically isolated from all gate contacts of the neighboring memory cell. The SRAM cell also includes a second conductive layer including a wordline coupled to the wordline landing pad in the first conductive layer. The SRAM cell further includes a first via coupling a gate contact of a pass transistor gate in the SRAM cell to the wordline landing pad in the first conductive layer. The SRAM cell also includes a second via coupling the wordline landing pad and the wordline of the second conductive layer.

Abstract translation: 静态随机存取存储器（SRAM）单元包括第一导电层，其包括延伸到存储器阵列的相邻行中的相邻存储器单元的字线着陆焊盘。 第一导电层中的字线着陆焊盘与相邻存储器单元的所有栅极触点电隔离。 SRAM单元还包括第二导电层，其包括耦合到第一导电层中的字线着陆焊盘的字线。 SRAM单元进一步包括将SRAM单元中的通过晶体管栅极的栅极接触耦合到第一导电层中的字线着陆焊盘的第一通孔。 SRAM单元还包括耦合字线着陆焊盘和第二导电层的字线的第二通孔。

公开(公告)号：US20150317426A1

公开(公告)日：2015-11-05

申请号：US14498939

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Niladri Narayan MOJUMDER ,  Zhongze WANG ,  Choh Fei YEAP

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/505 ,  G06F2217/78 ,  G06F2217/84

Abstract: Integrated circuit (IC) technology design may include binning data paths of an IC device of a current technology node to bins based on a performance of each of the data paths. Each of the plurality of bins is mapped to a representative circuit unit data path configured according to a predetermined set of electrical and/or physical parameters. The representative circuit unit data paths are calibrated according to updated electrical and/or physical parameters to increase the performance of the representative circuit unit data paths to improve the performance of the IC device in an advanced technology node.

Abstract translation: 集成电路（IC）技术设计可以包括基于每个数据路径的性能来对当前技术节点的IC设备的分组数据路径进行分组。 多个箱中的每一个被映射到根据预定的一组电和/或物理参数配置的代表性电路单元数据路径。 代表性的电路单元数据路径根据更新的电和/或物理参数进行校准，以增加代表性电路单元数据路径的性能，以提高先进技术节点中的IC器件的性能。

公开(公告)号：US20160133634A1

公开(公告)日：2016-05-12

申请号：US14995195

申请日：2016-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： Niladri Narayan MOJUMDER ,  Stanley Seungchul SONG ,  Zhongze WANG ,  Choh Fei YEAP

IPC: H01L27/11 ,  H01L29/423 ,  H01L27/105

CPC classification number: H01L27/1052 ,  G11C11/412 ,  H01L27/1104 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/785

Abstract: A complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cell. A CMOS SRAM cell in accordance with an aspect of the present disclosure includes a bit line and a word line. Such a CMOS SRAM memory cell further includes a CMOS memory cell having at least a first p-channel device comprising a first channel material that differs from a substrate material of the CMOS memory cell, the first channel material having an intrinsic channel mobility greater than the intrinsic channel mobility of the substrate material, the first p-channel device coupling the CMOS memory cell to the bit line and the word line.

公开(公告)号：US20160043092A1

公开(公告)日：2016-02-11

申请号：US14454805

申请日：2014-08-08

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan MOJUMDER ,  Stanley Seungchul SONG ,  Zhongze WANG ,  Choh Fei YEAP

IPC: H01L27/11

CPC classification number: H01L27/1052 ,  G11C11/412 ,  H01L27/1104 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/785

Abstract: A complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cell. A CMOS SRAM cell in accordance with an aspect of the present disclosure includes a bit line and a word line. Such a CMOS SRAM memory cell further includes a CMOS memory cell having at least a first p-channel device comprising a first channel material that differs from a substrate material of the CMOS memory cell, the first channel material having an intrinsic channel mobility greater than the intrinsic channel mobility of the substrate material, the first p-channel device coupling the CMOS memory cell to the bit line and the word line.

Abstract translation: 互补金属氧化物半导体（CMOS）静态随机存取存储器（SRAM）单元。 根据本公开的一个方面的CMOS SRAM单元包括位线和字线。 这种CMOS SRAM存储单元还包括具有至少第一p沟道器件的CMOS存储器单元，该第一p沟道器件包括与CMOS存储器单元的衬底材料不同的第一沟道材料，第一沟道材料具有大于 衬底材料的固有沟道迁移率，第一p沟道器件将CMOS存储器单元耦合到位线和字线。