公开(公告)号：US20180197743A1

公开(公告)日：2018-07-12

申请号：US15910929

申请日：2018-03-02

Applicant: QUALCOMM Incorporated

Inventor： Da YANG ,  Yanxiang LIU ,  Jun YUAN ,  Kern RIM

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/28123 ,  H01L29/66795 ,  H01L29/7851

Abstract: Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.

公开(公告)号：US20200161189A1

公开(公告)日：2020-05-21

申请号：US16752157

申请日：2020-01-24

Applicant: QUALCOMM Incorporated

Inventor： Stanley SONG ,  Jeffrey XU ,  Da YANG ,  Kern RIM ,  Choh fei YEAP

IPC: H01L21/8238 ,  H01L29/10 ,  H01L27/092 ,  H01L21/3065 ,  H01L29/66

Abstract: A method of producing a FinFET device with fin pitch of less than 20 nm is presented. In accordance with some embodiments, fins are deposited on sidewall spacers, which themselves are deposited on mandrels. The mandrels can be formed by lithographic processes while the fins and sidewall spacers formed by deposition technologies.

公开(公告)号：US20170077090A1

公开(公告)日：2017-03-16

申请号：US14852954

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Kern RIM ,  Jeffrey Junhao XU ,  John Jianhong ZHU ,  Jun CHEN ,  Da YANG ,  Choh Fei YEAP

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823475 ,  H01L29/0696 ,  H01L29/66545

Abstract: A multi-cell transistor includes gate body elements, gate tip elements extending from the gate body elements, and gate extensions extending from the gate tip elements. A patterned metal layer is provided between adjacent gate elements and at least portions of adjacent gate tip elements. Spacers are provided on the sides of each gate body element and each gate tip element to prevent the patterned metal layer from creating a short circuit between adjacent gate tip elements.

Abstract translation: 多单元晶体管包括门体元件，从栅极体元件延伸的栅极尖端元件以及从栅极尖端元件延伸的栅极延伸。 在相邻的栅极元件和相邻栅极尖端元件的至少一部分之间提供图案化的金属层。 隔板设置在每个门体元件和每个门尖元件的侧面上，以防止图案化的金属层在相邻的门尖元件之间产生短路。

公开(公告)号：US20180082906A1

公开(公告)日：2018-03-22

申请号：US15271043

申请日：2016-09-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley SONG ,  Jeffrey XU ,  Da YANG ,  Kern RIM ,  Choh fei YEAP

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L21/3065

Abstract: A method of producing a FinFET device with fin pitch of less than 20 nm is presented. In accordance with some embodiments, fins are deposited on sidewall spacers, which themselves are deposited on mandrels. The mandrels can be formed by lithographic processes while the fins and sidewall spacers formed by deposition technologies.

公开(公告)号：US20160126137A1

公开(公告)日：2016-05-05

申请号：US14993065

申请日：2016-01-11

Applicant: QUALCOMM Incorporated

Inventor： John J. ZHU ,  Zhongze WANG ,  Da YANG

IPC: H01L21/768

CPC classification number: H01L21/76894 ,  G03F7/7045 ,  G03F7/70466 ,  H01L21/28123 ,  H01L21/283 ,  H01L21/31 ,  H01L21/469 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/50 ,  H01L24/27 ,  H01L24/31 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip. A method includes patterning a first portion of a feature (such as a local interconnect) and a second portion of the feature to be separated by a predetermined distance, such as a line tip to tip space or a line space. The method further includes patterning the first portion with a cut mask to form a first sub-portion (e.g., a contact) and a second sub-portion. A dimension of the first sub-portion is less than a dimension of a second predetermined distance, which may be a line length resolution of a lithographic process having a specified width resolution. A feature of a semiconductor device includes a first portion and a second portion having a dimension less than a lithographic resolution of the first portion.

Abstract translation: 特征是在半导体芯片上制造的。 这些特征小于用于制造芯片的光刻的阈值。 一种方法包括图案化特征（例如局部互连）的第一部分和要分离预定距离的特征的第二部分，例如线尖到尖端空间或线空间。 该方法还包括用切割掩模图案化第一部分以形成第一子部分（例如，接触）和第二子部分。 第一子部分的尺寸小于第二预定距离的尺寸，其可以是具有指定宽度分辨率的光刻工艺的线长分辨率。 半导体器件的特征包括具有小于第一部分的光刻分辨率的尺寸的第一部分和第二部分。

公开(公告)号：US20180082846A1

公开(公告)日：2018-03-22

申请号：US15271867

申请日：2016-09-21

Applicant: QUALCOMM Incorporated

Inventor： Da YANG ,  Yanxiang LIU ,  Jun YUAN ,  Kern RIM

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3213

CPC classification number: H01L21/28123 ,  H01L21/32139 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.

公开(公告)号：US20160093511A1

公开(公告)日：2016-03-31

申请号：US14496365

申请日：2014-09-25

Applicant: QUALCOMM Incorporated

Inventor： Samit SENGUPTA ,  Shashank EKBOTE ,  Da YANG ,  Choh Fei YEAP

IPC: H01L21/3213 ,  H01L21/762 ,  H01L27/088

CPC classification number: H01L21/32139 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886

Abstract: A multigate transistor device such as a fin-shaped field effect transistor (FinFET) is fabricated by applying a self-aligned diffusion break (SADB) mask having an opening positioned to expose an area of at least one portion of at least one gate stripe designated as at least one tie-off gate in the multigate transistor device and removing the tie-off gate through the opening of the SADB mask to isolate transistors adjacent to the tie-off gate.

Abstract translation: 通过施加具有开口的自对准扩散断裂（SADB）掩模来制造诸如鳍状场效应晶体管（FinFET）的多栅晶体管器件，所述掩模被定位成暴露指定的至少一个栅极条的至少一部分的区域 作为多栅极晶体管器件中的至少一个截止栅极，并且通过SADB掩模的开口去除关断栅极，以隔离与截止栅极相邻的晶体管。

公开(公告)号：US20190304919A1

公开(公告)日：2019-10-03

申请号：US15936964

申请日：2018-03-27

Applicant: QUALCOMM Incorporated

Inventor： John ZHU ,  Da YANG ,  Stanley Seungchul SONG ,  Kern RIM

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/285

Abstract: Aspects of the disclosure are directed to an integrated circuit. The integrated circuit may include a metal contact comprising a first hybrid interconnect structure disposed within a metallization layer, and a metal comprising a second hybrid interconnect structure disposed within the metallization layer, wherein each of the first and the second hybrid interconnect structures has a top portion and a bottom portion, and wherein the top portion of each of the first and the second hybrid interconnect structures comprises a metal element that is suitable for chemical mechanical planarization (CMP) and the bottom portion of each of the first and the second hybrid interconnect structures comprises ruthenium (Ru). The metal element may comprise cobalt (Co).

公开(公告)号：US20160148936A1

公开(公告)日：2016-05-26

申请号：US14673485

申请日：2015-03-30

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  Stanley Seungchul SONG ,  Vladimir MACHKAOUTSAN ,  Mustafa BADAROGLU ,  Junjing BAO ,  John Jianhong ZHU ,  Da YANG ,  Choh Fei YEAP

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L29/24 ,  H01L29/417 ,  H01L29/08 ,  H01L29/06 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L27/0924 ,  H01L21/285 ,  H01L21/76897 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device includes a gate stack. The semiconductor device also includes a wrap-around contact arranged around and contacting substantially all surface area of a regrown source/drain region of the semiconductor device proximate to the gate stack.

Abstract translation: 半导体器件包括栅极堆叠。 该半导体器件还包括环绕接触件，布置在靠近栅极堆叠处的半导体器件的再生长源极/漏极区域的基本上所有的表面区域附近。