公开(公告)号：US20220398206A1

公开(公告)日：2022-12-15

申请号：US17809688

申请日：2022-06-29

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/00 ,  G06F13/00

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

公开(公告)号：US11409682B2

公开(公告)日：2022-08-09

申请号：US16950861

申请日：2020-11-17

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/00 ,  G06F13/00

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

公开(公告)号：US11106542B2

公开(公告)日：2021-08-31

申请号：US16593305

申请日：2019-10-04

Applicant: Rambus Inc.

Inventor： Steven Woo ,  David A. Secker ,  Ravindranath Kollipara

IPC: G06F11/14 ,  G06F1/12 ,  G06F11/16 ,  G06F11/20 ,  G06F13/42

Abstract: Described is memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.

公开(公告)号：US20200026677A1

公开(公告)日：2020-01-23

申请号：US16525315

申请日：2019-07-29

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/00 ,  G06F13/00

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

公开(公告)号：US10437685B2

公开(公告)日：2019-10-08

申请号：US15783177

申请日：2017-10-13

Applicant: Rambus Inc.

Inventor： Steven Woo ,  David A. Secker ,  Ravindranath Kollipara

IPC: G06F11/14 ,  G06F1/12 ,  G06F11/20 ,  G06F11/16 ,  G06F13/42

Abstract: Described is memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.

公开(公告)号：US10255220B2

公开(公告)日：2019-04-09

申请号：US15051554

申请日：2016-02-23

Applicant: Rambus Inc.

Inventor： Chi-Ming Yeung ,  David Secker ,  Ravindranath Kollipara ,  Shajith Musaliar Sirajudeen ,  Yoshie Nakabayashi

IPC: G06F13/00 ,  G06F13/40

Abstract: System and method for dynamic termination control to enable use of an increased number of memory modules on a single channel. In some embodiments, six or eight DIMMs are coupled to a single channel. The dynamic termination scheme can include configurations for input bus termination (IBT) on each of the memory modules for the address bus/command bus and configurations for on-die termination (ODT) one each of the memory modules for the data bus.

公开(公告)号：US20180285013A1

公开(公告)日：2018-10-04

申请号：US15745396

申请日：2016-07-14

Applicant: Rambus Inc.

Inventor： Suresh Rajan ,  Abhijit M. Abhyankar ,  Ravindranath Kollipara ,  David A. Secker

IPC: G06F3/06 ,  G06F13/16

Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.

公开(公告)号：US20180089035A1

公开(公告)日：2018-03-29

申请号：US15783177

申请日：2017-10-13

Applicant: Rambus Inc.

Inventor： Steven Woo ,  David A. Secker ,  Ravindranath Kollipara

IPC: G06F11/14 ,  G06F11/16

CPC classification number: G06F11/1456 ,  G06F1/12 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2058 ,  G06F13/4234 ,  G06F2201/84 ,  Y02D10/14 ,  Y02D10/151

Abstract: Described is memory system enabling memory minoring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.

公开(公告)号：US20140347092A1

公开(公告)日：2014-11-27

申请号：US14368772

申请日：2012-12-22

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Farshid Aryanfar ,  Ravindranath Kollipara ,  Xingchao (Chuck) Yuan

IPC: H03K19/00

CPC classification number: H03K19/0005 ,  G06F13/4086 ,  G11C29/50008 ,  H03K19/017545 ,  H04L25/0278

Abstract: Alternating on-die termination impedances are applied within an integrated circuit device to up-convert signal reflections to higher frequencies that are attenuated by the signaling channel as the reflections propagate toward an intended signal receiver. Through this approach, the disruptive effect of reflected signals may be significantly reduced with relatively little overhead within the interconnected integrated circuit devices and little or no change to the printed circuit board or other interconnect medium. Changes to the printed circuit board or other interconnect medium can be made to further increase attenuation over the frequency band of the up-converted reflection and outside of the transmission band of signals of interest.

Abstract translation: 在集成电路器件内施加交替的片上终端阻抗，以将信号反射上变频到由信号通道衰减的较高频率，因为反射向预期信号接收器传播。 通过这种方法，相互连接的集成电路器件内的相对较少的开销可以显着降低反射信号的破坏性影响，并且对印刷电路板或其它互连介质几乎没有或没有改变。 可以对印刷电路板或其它互连介质进行改变，以进一步增加在上变频反射的频带和感兴趣的信号的传输频带之外的衰减。