公开(公告)号：US20160204192A1

公开(公告)日：2016-07-14

申请号：US14965899

申请日：2015-12-11

Applicant: Renesas Electronics Corporation

Inventor： Yuya ABIKO ,  Satoshi EGUCHI ,  Akio ICHIMURA ,  Natsuo YAMAGUCHI ,  Tetsuya IIDA

IPC: H01L29/06 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/417

CPC classification number: H01L29/0696 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823487 ,  H01L27/0688 ,  H01L29/06 ,  H01L29/0634 ,  H01L29/0684 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/66727 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7811

Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

Abstract translation: 在包括p型列和n型列周期性排列的超结结构的半导体器件中，形成半导体元件的单元区域中的p型列区的深度比深度 在围绕细胞区域的中间区域中的p型列区域。 由此，电池区域的击穿电压变得低于中间区域的击穿电压。 即使在产生雪崩电流的电池区域中，优先发生雪崩击穿现象，电流分散而平稳地流动。 由此，能够避免局部的电流收缩和附带的断线，能够提高雪崩电阻（半导体装置的崩溃电流量的破坏）。

公开(公告)号：US20150333118A1

公开(公告)日：2015-11-19

申请号：US14705057

申请日：2015-05-06

Applicant: Renesas Electronics Corporation

Inventor： Satoshi EGUCHI ,  Tetsuya IIDA ,  Akio ICHIMURA ,  Yuya ABIKO

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7811 ,  H01L21/265 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/66477 ,  H01L29/66712

Abstract: To provide a semiconductor device including a power semiconductor element having improved reliability. The semiconductor device has a cell region and a peripheral region formed outside the cell region. The n type impurity concentration of n type column regions in the cell region is made higher than that of n type column regions comprised of an epitaxial layer in the peripheral region. Further, a charge balance is kept in each of the cell region and the peripheral region and each total electric charge is set so that a total electric charge of first p type column regions and a total electric charge of n type column regions in the cell region become larger than a total electric charge of third p type column regions and n type column regions comprised of an epitaxial layer in the peripheral region, respectively.

Abstract translation: 提供包括具有提高的可靠性的功率半导体元件的半导体器件。 半导体器件具有形成在单元区域外的单元区域和周边区域。 使单元区域中的n型列区域的n型杂质浓度高于在外围区域中由外延层构成的n型列区域的n型杂质浓度。 此外，在单元区域和外围区域中的每一个中保持电荷平衡，并且设置每个总电荷，使得第一p型列区域的总电荷和单元区域中的n型列区域的总电荷 分别变得大于第三p型列区域的总电荷和由周边区域中的外延层构成的n型列区域。

公开(公告)号：US20140299961A1

公开(公告)日：2014-10-09

申请号：US14309651

申请日：2014-06-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomohiro TAMAKI ,  Yoshito NAKAZAWA ,  Satoshi EGUCHI

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/7811 ,  H01L27/088 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7396

Abstract: A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.

Abstract translation: 解决超结结构的以下问题的半导体装置：由于体细胞区域（有源区域）的相对高的浓度，在周边区域（周边区域或结合区域）中难以实现击穿电压 等于或高于通过常规的连接边缘端子结构或再结构的单元区域。 半导体器件包括通过沟槽填充技术在单元区域中形成的具有超结结构的功率MOSFET。 此外，在细胞区域周围的漂移区域中设置具有与细胞区域的侧面平行的取向的超结结构。

公开(公告)号：US20140120669A1

公开(公告)日：2014-05-01

申请号：US14149909

申请日：2014-01-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Satoshi EGUCHI ,  Yuya ABIKO ,  Junichi KOGURE

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7802 ,  H01L21/02639 ,  H01L21/26506 ,  H01L21/26566 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7842 ,  H01L29/7848

Abstract: In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth.

公开(公告)号：US20130264650A1

公开(公告)日：2013-10-10

申请号：US13910352

申请日：2013-06-05

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro TAMAKI ,  Yoshito NAKAZAWA ,  Satoshi EGUCHI

IPC: H01L27/088

CPC classification number: H01L29/7811 ,  H01L27/088 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7396

Abstract: A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.

Abstract translation: 解决超结结构的以下问题的半导体装置：由于体细胞区域（有源区域）的相对高的浓度，在周边区域（周边区域或结合区域）中难以实现击穿电压 等于或高于通过常规的连接边缘端子结构或再结构的单元区域。 半导体器件包括通过沟槽填充技术在单元区域中形成的具有超结结构的功率MOSFET。 此外，在细胞区域周围的漂移区域中设置具有与细胞区域的侧面平行的取向的超结结构。