公开(公告)号：US20180047843A1

公开(公告)日：2018-02-15

申请号：US15792876

申请日：2017-10-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomohiro TAMAKI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/739 ,  H01L29/868 ,  H01L29/40 ,  H01L29/861 ,  H01L29/872 ,  H01L29/417 ,  H01L29/10 ,  H01L29/16

CPC classification number: H01L29/7811 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7396 ,  H01L29/8611 ,  H01L29/868 ,  H01L29/872

Abstract: Super-junction MOSFETs by trench fill system requires void-free filling epitaxial growth. This may require alignment of plane orientations of trenches in a given direction. Particularly, when column layout at chip corner part is bilaterally asymmetrical with a diagonal line between chip corners, equipotential lines in a blocking state are curved at corner parts due to column asymmetry at chip corner. This tends to cause points where equipotential lines become dense, which may cause breakdown voltage reduction. In the present invention, in power type semiconductor active elements such as power MOSFETs, a ring-shaped field plate is disposed in chip peripheral regions around an active cell region, etc., assuming a nearly rectangular shape. The field plate has an ohmic-contact part in at least a part of the portion along the side of the rectangle. However, in the portion corresponding to the corner part of the rectangle, an ohmic-contact part is not disposed.

公开(公告)号：US20140191309A1

公开(公告)日：2014-07-10

申请号：US14109208

申请日：2013-12-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Satoshi EGUCHI ,  Yoshito NAKAZAWA ,  Tomohiro TAMAKI

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0619 ,  H01L29/0626 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811

Abstract: When forming a super junction by the embedded epitaxial method, adjusting a taper angle of dry etching to form an inclined column is generally performed in trench forming etching, in order to prevent a reduction in breakdown voltage due to fluctuations in concentration in an embedded epitaxial layer. However, according to the examination by the present inventors, it has been made clear that such a method makes design more and more difficult in response to the higher breakdown voltage. In the present invention, the concentration in an intermediate substrate epitaxy column area in each substrate epitaxy column area configuring a super junction is made more than that in other areas within the substrate epitaxy column area, in a vertical power MOSFET having the super junction by the embedded epitaxial method.

Abstract translation: 当通过嵌入式外延法形成超级结时，通常在沟槽形成蚀刻中进行干蚀刻的锥角调整以形成倾斜的列，以便防止由嵌入的外延层中的浓度波动引起的击穿电压的降低 。 然而，根据本发明人的考察，已经清楚的是，这种方法使得设计越来越难以响应较高的击穿电压。 在本发明中，在构成超结的每个衬底外延柱区域中的中间衬底外延柱区域中的浓度比在衬底外延柱区域内的其它区域的浓度高， 嵌入式外延法。

公开(公告)号：US20160190235A1

公开(公告)日：2016-06-30

申请号：US15062029

申请日：2016-03-04

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro TAMAKI ,  Yoshito NAKAZAWA

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/66681 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7823 ,  H01L29/7825

Abstract: A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.

公开(公告)号：US20150155378A1

公开(公告)日：2015-06-04

申请号：US14622163

申请日：2015-02-13

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro TAMAKI ,  Yoshito NAKAZAWA

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L29/7811 ,  H01L23/3107 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7816 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/29099

Abstract: In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region.

Abstract translation: 在诸如在有源单元区域和芯片外围区域中的每一个中具有超结结构的功率MOSFET的半导体功率器件中，第二导电类型的表面区域的外端与第二导电性的主结 类型在第一导电类型的漂移区的表面中并且具有低于主结的浓度的漂移区的表面位于主结的外端和超结结构的外端之间的中间区域 芯片外围区域。

公开(公告)号：US20140110779A1

公开(公告)日：2014-04-24

申请号：US14027956

申请日：2013-09-16

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro TAMAKI

IPC: H01L29/78

CPC classification number: H01L29/7811 ,  H01L21/046 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

Abstract: Vertical power MOSFETs having a super junction are devices capable of having a lower on resistance than other vertical power MOSFETs. Although they have the advantage of high-speed switching due to rapid depletion of an N type drift region at the time of turn off in switching operation, they are likely to cause ringing. A vertical power MOSFET having a super junction structure provided by the present invention has, in the surface region of a first conductivity type drift region under a gate electrode, an undergate heavily doped N type region having a depth shallower than that of a second conductivity type body region and having a concentration higher than that of the first conductivity type drift region.

Abstract translation: 具有超级结的垂直功率MOSFET是能够比其他垂直功率MOSFET具有更低导通电阻的器件。 虽然它们具有由于切换操作中的关闭时N型漂移区的快速耗尽而具有高速切换的优点，但是它们可能引起振铃。 本发明提供的具有超结结构的垂直功率MOSFET在栅电极下的第一导电类型漂移区的表面区域具有深度比第二导电类型深的浅底栅重掺杂N型区 并且其浓度高于第一导电类型漂移区域的浓度。

公开(公告)号：US20160035880A1

公开(公告)日：2016-02-04

申请号：US14855980

申请日：2015-09-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomohiro TAMAKI

IPC: H01L29/78 ,  H01L29/40

CPC classification number: H01L29/7811 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7396 ,  H01L29/8611 ,  H01L29/868 ,  H01L29/872

Abstract: Super-junction MOSFETs by trench fill system requires void-free filling epitaxial growth. This may require alignment of plane orientations of trenches in a given direction. Particularly, when column layout at chip corner part is bilaterally asymmetrical with a diagonal line between chip corners, equipotential lines in a blocking state are curved at corner parts due to column asymmetry at chip corner. This tends to cause points where equipotential lines become dense, which may cause breakdown voltage reduction. In the present invention, in power type semiconductor active elements such as power MOSFETs, a ring-shaped field plate is disposed in chip peripheral regions around an active cell region, etc., assuming a nearly rectangular shape. The field plate has an ohmic-contact part in at least a part of the portion along the side of the rectangle. However, in the portion corresponding to the corner part of the rectangle, an ohmic-contact part is not disposed.

公开(公告)号：US20140027842A1

公开(公告)日：2014-01-30

申请号：US14037103

申请日：2013-09-25

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro TAMAKI ,  Yoshito NAKAZAWA

IPC: H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/66681 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7823 ,  H01L29/7825

Abstract: A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.

Abstract translation: 解决了与各种工艺参数相对较轻的波动引起的n沟道功率MOSFET等相关的问题：源极 - 漏极击穿电压通过靠近p型体区域的端部的击穿而减小 到由该区域的电场浓度引起的活性单元区域与芯片周边部分之间的环状中间区域附近的部分。 为了解决这个问题，在第一导电类型的有源电池区域，芯片外围区域和位于它们之间的中间区域的各个漂移区域中，具有超结构结构的功率半导体器件采取以下措施： 使包括中间区域中的超结构结构的第二导电类型的列区域中的至少一个比其它区域的宽度大。

公开(公告)号：US20170069751A1

公开(公告)日：2017-03-09

申请号：US15355583

申请日：2016-11-18

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro TAMAKI

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/417 ,  H01L21/04 ,  H01L29/16 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7811 ,  H01L21/046 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

Abstract: Vertical power MOSFETs having a super junction are devices capable of having a lower on resistance than other vertical power MOSFETs. Although they have the advantage of high-speed switching due to rapid depletion of an N type drift region at the time of turn off in switching operation, they are likely to cause ringing. A vertical power MOSFET having a super junction structure provided by the present invention has, in the surface region of a first conductivity type drift region under a gate electrode, an undergate heavily doped N type region having a depth shallower than that of a second conductivity type body region and having a concentration higher than that of the first conductivity type drift region.

Abstract translation: 具有超级结的垂直功率MOSFET是能够比其他垂直功率MOSFET具有更低导通电阻的器件。 虽然它们具有由于切换操作中的关闭时N型漂移区的快速耗尽而具有高速切换的优点，但是它们可能引起振铃。 本发明提供的具有超结结构的垂直功率MOSFET在栅电极下的第一导电类型漂移区的表面区域具有深度比第二导电类型深的浅底栅重掺杂N型区 并且其浓度高于第一导电类型漂移区域的浓度。

公开(公告)号：US20160126345A1

公开(公告)日：2016-05-05

申请号：US14993671

申请日：2016-01-12

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro TAMAKI ,  Yoshito Nakazawa ,  Satoshi Eguchi

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/7811 ,  H01L27/088 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7396

Abstract: A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.

Abstract translation: 解决超结结构的以下问题的半导体装置：由于体细胞区域（有源区域）的相对高的浓度，在周边区域（周边区域或结合区域）中难以实现击穿电压 等于或高于通过常规的连接边缘端子结构或再结构的单元区域。 半导体器件包括通过沟槽填充技术在单元区域中形成的具有超结结构的功率MOSFET。 此外，在细胞区域周围的漂移区域中设置具有与细胞区域的侧面平行的取向的超结结构。

公开(公告)号：US20140299961A1

公开(公告)日：2014-10-09

申请号：US14309651

申请日：2014-06-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tomohiro TAMAKI ,  Yoshito NAKAZAWA ,  Satoshi EGUCHI

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/7811 ,  H01L27/088 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7396

Abstract: A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region.

Abstract translation: 解决超结结构的以下问题的半导体装置：由于体细胞区域（有源区域）的相对高的浓度，在周边区域（周边区域或结合区域）中难以实现击穿电压 等于或高于通过常规的连接边缘端子结构或再结构的单元区域。 半导体器件包括通过沟槽填充技术在单元区域中形成的具有超结结构的功率MOSFET。 此外，在细胞区域周围的漂移区域中设置具有与细胞区域的侧面平行的取向的超结结构。