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公开(公告)号：US09722044B2
公开(公告)日：2017-08-01
申请号：US14990242
申请日：2016-01-07
IPC分类号： H01L29/66 , H01L29/36 , H01L21/365 , H01L21/324 , H01L29/06 , H01L29/786 , H01L21/84 , H01L27/12 , H01L21/265
CPC分类号： H01L29/66537 , H01L21/265 , H01L21/26506 , H01L21/2652 , H01L21/324 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/0649 , H01L29/36 , H01L29/66492 , H01L29/66742 , H01L29/7833 , H01L29/78603 , H01L29/78684
摘要： A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.
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公开(公告)号：US09484433B2
公开(公告)日：2016-11-01
申请号：US14929646
申请日：2015-11-02
IPC分类号： H01L21/00 , H01L29/66 , H01L29/786 , H01L27/12 , H01L29/417 , H01L29/423 , H01L29/78 , H01L21/768 , H01L29/08 , H01L21/8238 , H01L21/84 , H01L21/265
CPC分类号： H01L29/1083 , H01L21/265 , H01L21/74 , H01L21/76897 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/0878 , H01L29/41783 , H01L29/4238 , H01L29/66477 , H01L29/665 , H01L29/66537 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66742 , H01L29/66757 , H01L29/66772 , H01L29/7824 , H01L29/7833 , H01L29/78606 , H01L29/78621 , H01L29/78651 , H01L29/78654
摘要： Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
摘要翻译： 在SOI衬底上的栅电极的侧壁上形成具有通过依次层叠氧化硅膜和氮化物膜而获得的堆叠结构的侧壁。 随后，在栅极旁边形成外延层之后，去除氮化物膜。 然后，使用栅电极和外延层作为掩模将杂质注入到半导体衬底的上表面中，使得仅在半导体衬底的上表面的正下方形成晕圈区域 栅电极的两端附近。
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公开(公告)号：US09460936B2
公开(公告)日：2016-10-04
申请号：US14856382
申请日：2015-09-16
IPC分类号： H01L21/32 , H01L29/66 , H01L29/78 , H01L29/423 , H01L29/786 , H01L29/08
CPC分类号： H01L21/32 , H01L29/0847 , H01L29/42376 , H01L29/42384 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66772 , H01L29/78 , H01L29/7834 , H01L29/7836 , H01L29/7848 , H01L29/786 , H01L29/78618 , H01L29/78627
摘要： The semiconductor device has a gate electrode GE formed on a substrate via a gate insulating film GI and a source/drain semiconductor layer EP1 formed on the substrate. The upper surface of the semiconductor layer EP1 is positioned higher than the upper surface of the substrate straight below the gate electrode GE. And, end parts of the gate electrode GE in a gate length direction are positioned on the semiconductor layer EP1.
摘要翻译： 半导体器件具有通过形成在基板上的栅极绝缘膜GI和源极/漏极半导体层EP1在基板上形成的栅电极GE。 半导体层EP1的上表面比栅电极GE下方的基板的上表面高。 并且，栅极电极GE的栅极长度方向的端部位于半导体层EP1上。
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公开(公告)号：US09263346B2
公开(公告)日：2016-02-16
申请号：US14155708
申请日：2014-01-15
IPC分类号： H01L21/84 , H01L21/265 , H01L29/786 , H01L29/66 , H01L27/12
CPC分类号： H01L29/66537 , H01L21/265 , H01L21/26506 , H01L21/2652 , H01L21/324 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L29/0649 , H01L29/36 , H01L29/66492 , H01L29/66742 , H01L29/7833 , H01L29/78603 , H01L29/78684
摘要： A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.
摘要翻译： 具有在包括支撑衬底的SOI衬底上形成的n沟道MISFET的半导体器件，形成在支撑衬底上的绝缘层和形成在绝缘层上的硅层具有以下结构。 在栅电极的支撑基板上设置用于阈值调整的杂质区域，使得硅层含有碳。 可以通过半导体区域以这种方式调整阈值进行阈值调整。 此外，通过设置含有碳的硅层，即使当用于阈值调节的半导体区域的杂质扩散到穿过绝缘层的硅层时，通过注入到硅层中的碳使杂质失活。 结果，可以降低晶体管特性的波动，例如MISFET的阈值电压的波动。
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公开(公告)号：US09196705B2
公开(公告)日：2015-11-24
申请号：US14579242
申请日：2014-12-22
IPC分类号： H01L21/00 , H01L29/66 , H01L29/786 , H01L27/12 , H01L29/417 , H01L29/423 , H01L29/78 , H01L21/768 , H01L29/08 , H01L21/265
CPC分类号： H01L29/1083 , H01L21/265 , H01L21/74 , H01L21/76897 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/0878 , H01L29/41783 , H01L29/4238 , H01L29/66477 , H01L29/665 , H01L29/66537 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66742 , H01L29/66757 , H01L29/66772 , H01L29/7824 , H01L29/7833 , H01L29/78606 , H01L29/78621 , H01L29/78651 , H01L29/78654
摘要： Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
摘要翻译： 防止在SOI衬底上发生MOSFET的短沟道特性和寄生电容。 在SOI衬底上的栅电极的侧壁上形成具有通过依次层叠氧化硅膜和氮化物膜而获得的堆叠结构的侧壁。 随后，在栅极旁边形成外延层之后，去除氮化物膜。 然后，使用栅电极和外延层作为掩模，将杂质注入到半导体衬底的上表面中，使得仅在半导体衬底的上表面的正下方形成晕圈区域 栅电极的两端附近。
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公开(公告)号：US20130264644A1
公开(公告)日：2013-10-10
申请号：US13859297
申请日：2013-04-09
CPC分类号： H01L27/1203 , H01L21/823418 , H01L21/823814 , H01L27/1207 , H01L29/41783 , H01L29/66477 , H01L29/66628 , H01L29/66651 , H01L29/7834
摘要： On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.
摘要翻译： 在其上表面上形成有SOI区域和体硅区域的半导体衬底上，在形成于SOI区域的MOSFET的源极和漏极区域中形成外延层，在源极和漏极区域中不形成外延层 在体硅区域形成MOSFET。 通过用氮化硅膜覆盖外延层的端部，即使当通过从外延层上方注入离子形成扩散层时，也可以防止杂质离子注入到硅层的下表面。
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