公开(公告)号：US11695012B2

公开(公告)日：2023-07-04

申请号：US16928542

申请日：2020-07-14

Applicant: Renesas Electronics Corporation

Inventor： Takaaki Tsunomura ,  Yoshiki Yamamoto ,  Masaaki Shinohara ,  Toshiaki Iwamatsu ,  Hidekazu Oda

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L21/8238

CPC classification number: H01L27/1203 ,  H01L27/1207 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/41783

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US09633859B2

公开(公告)日：2017-04-25

申请号：US15043579

申请日：2016-02-14

Applicant: Renesas Electronics Corporation

Inventor： Tatsuyoshi Mihara ,  Masaaki Shinohara

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11568 ,  H01L27/11573

CPC classification number: H01L21/28282 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, a first insulation film, a conductive film, a silicon-containing second insulation film, and a third film formed of silicon are sequentially formed at the surface of a control gate electrode. Then, the third film is etched back to leave the third film at the side surface of the control gate electrode via the first insulation film, the conductive film, and the second insulation film, thereby to form a spacer. Then, the conductive film is etched back to form a memory gate electrode formed of the conductive film between the spacer and the control gate electrode, and between the spacer and the semiconductor substrate.

公开(公告)号：US10546946B2

公开(公告)日：2020-01-28

申请号：US15409947

申请日：2017-01-19

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara

IPC: H01L29/66

Abstract: Provided is a stable manufacturing method for a semiconductor device. In the manufacturing method for a semiconductor device, first, fins with an equal width are formed in each of a memory cell portion and a logic portion of a semiconductor substrate. Then, the fins in the logic portion are etched with the fins in the memory cell covered with a mask film, thereby fabricating fins in the logic portion, each of which is narrower than the fin formed in the memory cell portion.

公开(公告)号：US10163922B2

公开(公告)日：2018-12-25

申请号：US15468673

申请日：2017-03-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichiro Abe ,  Masaaki Shinohara

IPC: H01L29/792 ,  H01L27/1157 ,  H01L29/66

Abstract: In a MONOS memory, withstand voltage is increased between a control gate electrode over an ONO film having a charge accumulating part and a semiconductor substrate. When a silicon film is processed to form a control gate electrode, dry etching is performed for a relatively long time, thereby a recess is formed in a sidewall of the control gate electrode. Subsequently, the control gate electrode is subjected to dry oxidation treatment to form an insulating film on the sidewall of the control gate electrode including the recess, thereby an end of the bottom of the control gate electrode is separated from an end of the top of the ONO film.

公开(公告)号：US09960075B2

公开(公告)日：2018-05-01

申请号：US15497740

申请日：2017-04-26

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara ,  Satoshi Iida

IPC: H01L21/70 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/76224 ,  H01L21/308 ,  H01L21/76205 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film. The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

公开(公告)号：US09947679B2

公开(公告)日：2018-04-17

申请号：US14860700

申请日：2015-09-21

Applicant: Renesas Electronics Corporation

Inventor： Fukuo Owada ,  Masaaki Shinohara ,  Takahiro Maruyama

IPC: H01L27/115 ,  H01L27/11546 ,  H01L27/11529

CPC classification number: H01L27/11546 ,  H01L27/11529

Abstract: An improvement is achieved in the performance of a semiconductor device. Over a first insulating film formed over a main surface of a semiconductor substrate located in a memory formation region and having an internal charge storage portion and over a second insulating film formed over the main surface of the semiconductor substrate located in a main circuit formation region, a conductive film is formed. Then, in the memory formation region, the conductive film and the first insulating film are patterned to form a first gate electrode and a first gate insulating film while, in the main circuit formation region, the conductive film and the second insulating film are left. Then, in the main circuit formation region, the conductive film and the second insulating film are patterned to form a second gate electrode and a second gate insulating film.

公开(公告)号：US10109626B2

公开(公告)日：2018-10-23

申请号：US15455497

申请日：2017-03-10

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06

Abstract: To provide a semiconductor device having an element isolation structure formed in the main surface of a semiconductor substrate, having a space in a trench, and prevented from having deteriorated performance due to an increase in the height of the top portion of the space. A trench portion is formed in the main surface of a semiconductor substrate by using a hard-mask insulating film. A first insulating film that covers the upper surface of the hard-mask insulating film and the surface of the trench portion is formed, followed by etch-back of the first insulating film to expose the upper surface of the hard-mask insulating film. Then, second and third insulating films that cover the upper surface of the hard-mask insulating film and the surface of the trench portion are formed to form a space in the trench portion.

公开(公告)号：US09935125B2

公开(公告)日：2018-04-03

申请号：US13859297

申请日：2013-04-09

Applicant: Renesas Electronics Corporation

Inventor： Takaaki Tsunomura ,  Yoshiki Yamamoto ,  Masaaki Shinohara ,  Toshiaki Iwamatsu ,  Hidekazu Oda

IPC: H01L21/70 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L21/8238

CPC classification number: H01L27/1203 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/1207 ,  H01L29/41783 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US09418996B2

公开(公告)日：2016-08-16

申请号：US15053551

申请日：2016-02-25

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara ,  Satoshi Iida

IPC: H01L21/70 ,  H01L27/092 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/308 ,  H01L21/76205 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film.The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

Abstract translation: 在高击穿电压MOSFET中使用STI绝缘膜导致由于漏极隔离绝缘膜的底角附近的冲击电离导致的可靠性降低。 本发明提供一种半导体集成电路器件的制造方法，其包括在其侧表面上形成硬掩模膜，其中的开口和侧壁绝缘膜; 在所述开口中形成浅沟槽，所述硬掩模膜作为掩模，并至少氧化暴露部分; 用绝缘膜填充沟槽，然后将其移除，使其离开开口中的沟槽，从而在沟槽内部和外部形成漏极偏移STI绝缘膜; 以及形成从栅极绝缘膜的上部延伸的栅极电极与其邻接的有源区域延伸到漏极绝缘膜的上部。

公开(公告)号：US20160005640A1

公开(公告)日：2016-01-07

申请号：US14738846

申请日：2015-06-13

Applicant: Renesas Electronics Corporation

Inventor： Masaaki Shinohara ,  Satoshi Iida

IPC: H01L21/762 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L21/308 ,  H01L21/76205 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833

Abstract: Using an STI insulating film in a high breakdown voltage MOSFET leads to deterioration in reliability due to impact ionization near the bottom corner of a drain isolation insulating film.The invention provides a method of manufacturing a semiconductor integrated circuit device including forming a hard mask film, an opening therein, and a sidewall insulating film on the side surface thereof; forming a shallow trench in the opening with the hard mask film as a mask and oxidizing at least an exposed portion; filling the trench with an insulating film and then removing it so as to leave it outside the trench in the opening and thereby forming a drain offset STI insulating film inside and outside the trench; and forming a gate electrode extending from the upper portion of a gate insulating film in an active region contiguous thereto to the upper portion of the drain offset insulating film.

Abstract translation: 在高击穿电压MOSFET中使用STI绝缘膜导致由于漏极隔离绝缘膜的底角附近的冲击电离导致的可靠性降低。 本发明提供一种半导体集成电路器件的制造方法，其包括在其侧表面上形成硬掩模膜，其中的开口和侧壁绝缘膜; 在所述开口中形成浅沟槽，所述硬掩模膜作为掩模，并至少氧化暴露部分; 用绝缘膜填充沟槽，然后将其移除，使其离开开口中的沟槽，从而在沟槽内部和外部形成漏极偏移STI绝缘膜; 以及形成从栅极绝缘膜的上部延伸的栅极电极与其邻接的有源区域延伸到漏极绝缘膜的上部。