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公开(公告)号：US20160056264A1
公开(公告)日：2016-02-25
申请号：US14929646
申请日：2015-11-02
CPC分类号： H01L29/1083 , H01L21/265 , H01L21/74 , H01L21/76897 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/0878 , H01L29/41783 , H01L29/4238 , H01L29/66477 , H01L29/665 , H01L29/66537 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66742 , H01L29/66757 , H01L29/66772 , H01L29/7824 , H01L29/7833 , H01L29/78606 , H01L29/78621 , H01L29/78651 , H01L29/78654
摘要： Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
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公开(公告)号：US20150325673A1
公开(公告)日：2015-11-12
申请号：US14803040
申请日：2015-07-18
IPC分类号： H01L29/66 , H01L21/266 , H01L29/417
CPC分类号： H01L29/7827 , H01L21/266 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/66666 , H01L29/66772 , H01L29/78621
摘要： A semiconductor device is manufactured by using an SOI substrate having an insulating layer on a substrate and a semiconductor layer on the insulating layer. The semiconductor device is provided with a gate electrode formed on the semiconductor layer via a gate insulating film, a sidewall spacer formed on a sidewall of the gate electrode, a semiconductor layer for source/drain that is epitaxially grown on the semiconductor layer, and a sidewall spacer formed on a sidewall of the semiconductor layer.
摘要翻译： 通过使用在衬底上具有绝缘层的SOI衬底和绝缘层上的半导体层来制造半导体器件。 半导体器件设置有通过栅极绝缘膜形成在半导体层上的栅极电极，形成在栅电极的侧壁上的侧壁间隔物，在半导体层上外延生长的用于源极/漏极的半导体层，以及 侧壁间隔物形成在半导体层的侧壁上。
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公开(公告)号：US09130039B2
公开(公告)日：2015-09-08
申请号：US13962066
申请日：2013-08-08
IPC分类号： H01L29/76 , H01L29/78 , H01L29/66 , H01L29/417 , H01L29/786
CPC分类号： H01L29/7827 , H01L21/266 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/66666 , H01L29/66772 , H01L29/78621
摘要： A semiconductor device is manufactured by using an SOI substrate having an insulating layer on a substrate and a semiconductor layer on the insulating layer. The semiconductor device is provided with a gate electrode formed on the semiconductor layer via a gate insulating film, a sidewall spacer formed on a sidewall of the gate electrode, a semiconductor layer for source/drain that is epitaxially grown on the semiconductor layer, and a sidewall spacer formed on a sidewall of the semiconductor layer.
摘要翻译： 通过使用在衬底上具有绝缘层的SOI衬底和绝缘层上的半导体层来制造半导体器件。 半导体器件设置有通过栅极绝缘膜形成在半导体层上的栅电极，形成在栅电极的侧壁上的侧壁间隔物，在半导体层上外延生长的用于源极/漏极的半导体层，以及 侧壁间隔物形成在半导体层的侧壁上。
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公开(公告)号：US12080716B2
公开(公告)日：2024-09-03
申请号：US18317500
申请日：2023-05-15
IPC分类号： H01L27/12 , H01L29/66 , H01L29/78 , H01L21/8234 , H01L21/8238 , H01L29/417
CPC分类号： H01L27/1203 , H01L27/1207 , H01L29/66477 , H01L29/66628 , H01L29/66651 , H01L29/7834 , H01L21/823418 , H01L21/823814 , H01L29/41783
摘要： On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.
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公开(公告)号：US10756115B2
公开(公告)日：2020-08-25
申请号：US16670918
申请日：2019-10-31
IPC分类号： H01L21/8234 , H01L27/12 , H01L29/66 , H01L29/78 , H01L29/417 , H01L21/8238
摘要： On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.
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公开(公告)号：US10510775B2
公开(公告)日：2019-12-17
申请号：US15695410
申请日：2017-09-05
IPC分类号： H01L29/06 , H01L27/12 , H01L29/66 , H01L29/78 , H01L21/8234 , H01L29/417 , H01L21/8238
摘要： On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.
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公开(公告)号：US09978839B2
公开(公告)日：2018-05-22
申请号：US15628925
申请日：2017-06-21
IPC分类号： H01L21/00 , H01L29/10 , H01L29/78 , H01L29/06 , H01L21/74 , H01L29/66 , H01L21/265 , H01L21/8238 , H01L21/84
CPC分类号： H01L29/1083 , H01L21/265 , H01L21/74 , H01L21/76897 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/0878 , H01L29/41783 , H01L29/4238 , H01L29/66477 , H01L29/665 , H01L29/66537 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66742 , H01L29/66757 , H01L29/66772 , H01L29/7824 , H01L29/7833 , H01L29/78606 , H01L29/78621 , H01L29/78651 , H01L29/78654
摘要： Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
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公开(公告)号：US08941178B2
公开(公告)日：2015-01-27
申请号：US13747537
申请日：2013-01-23
IPC分类号： H01L27/12 , H01L29/786 , H01L29/66
CPC分类号： H01L29/1083 , H01L21/265 , H01L21/74 , H01L21/76897 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/0649 , H01L29/0847 , H01L29/0878 , H01L29/41783 , H01L29/4238 , H01L29/66477 , H01L29/665 , H01L29/66537 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66742 , H01L29/66757 , H01L29/66772 , H01L29/7824 , H01L29/7833 , H01L29/78606 , H01L29/78621 , H01L29/78651 , H01L29/78654
摘要： Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
摘要翻译： 防止在SOI衬底上发生MOSFET的短沟道特性和寄生电容。 在SOI衬底上的栅电极的侧壁上形成具有通过依次层叠氧化硅膜和氮化物膜而获得的堆叠结构的侧壁。 随后，在栅极旁边形成外延层之后，去除氮化物膜。 然后，使用栅电极和外延层作为掩模，将杂质注入到半导体衬底的上表面中，使得仅在半导体衬底的上表面的正下方形成晕圈区域 栅电极的两端附近。
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公开(公告)号：US10461158B2
公开(公告)日：2019-10-29
申请号：US16150323
申请日：2018-10-03
IPC分类号： H01L29/10 , H01L29/786 , H01L29/66 , H01L27/12 , H01L29/417 , H01L29/423 , H01L29/78 , H01L21/768 , H01L29/08 , H01L21/8238 , H01L21/84 , H01L21/265 , H01L29/06 , H01L21/74 , H01L21/8234
摘要： Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
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公开(公告)号：US10411112B2
公开(公告)日：2019-09-10
申请号：US15634439
申请日：2017-06-27
IPC分类号： H01L21/265 , H01L21/84 , H01L27/12 , H01L29/78 , H01L29/786 , H01L29/66 , H01L29/36 , H01L21/324 , H01L29/06 , H01L21/8238 , H01L27/092
摘要： A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.
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