公开(公告)号：US20130107769A1

公开(公告)日：2013-05-02

申请号：US13661164

申请日：2012-10-26

Applicant: RF Micro Devices, Inc.

Inventor： Nadim Khlat ,  Christopher Truong Ngo

IPC: H04L27/06 ,  H04J11/00

CPC classification number: H03F1/0227 ,  H02M3/156 ,  H03F3/19 ,  H03F2200/108 ,  H03F2200/351

Abstract: This disclosure relates generally to radio frequency (RF) switching converters and RF amplification devices that use RF switching converters. For example, an RF switching converter may include a switching circuit that receives a power source voltage and a switching controller that receives a target average frequency value identifying a target average frequency. The switching circuit is switchable so as to generate a pulsed output voltage from the power source voltage. The switching controller switches the switching circuit such that the pulsed output voltage has an average pulse frequency. The switching controller also detects that the average pulse frequency of the pulsed output voltage during a time period differs from the target average frequency, and reduces a difference between the average pulse frequency and the target average frequency. In this manner, the effects of manufacturing variations and operational variations on the average pulse frequency can be eliminated, or at least diminished.

Abstract translation: 本公开一般涉及使用RF开关转换器的射频（RF）开关转换器和RF放大器件。 例如，RF开关转换器可以包括接收电源电压的开关电路和接收识别目标平均频率的目标平均频率值的开关控制器。 开关电路是可切换的，以便从电源电压产生脉冲输出电压。 开关控制器切换开关电路，使得脉冲输出电压具有平均脉冲频率。 切换控制器还检测在一段时间内脉冲输出电压的平均脉冲频率与目标平均频率不同，并且减小了平均脉冲频率和目标平均频率之间的差。 以这种方式，可以消除或至少减少制造变化和操作变化对平均脉冲频率的影响。

公开(公告)号：US10528502B2

公开(公告)日：2020-01-07

申请号：US14659371

申请日：2015-03-16

Applicant: RF Micro Devices, Inc.

Inventor： Christopher Truong Ngo ,  Alexander Wayne Hietala ,  Christian Rye Iversen ,  Ruediger Bauder

IPC: G06F13/364

Abstract: Embodiments of bus interface systems are disclosed. In one embodiment, a bus interface system includes a master bus controller and a slave bus controller coupled along a bus line. The master bus controller is configured to generate an input data signal that is received by the slave bus controller along the bus line. The slave bus controller includes power conversion circuitry configured to convert the input data signal from the master bus controller into a supply voltage. By providing the power conversion circuitry, the slave bus controller is powered using the input data signal and without requiring an additional bus line to transfer a supply voltage to the slave bus controller.

公开(公告)号：US10185683B2

公开(公告)日：2019-01-22

申请号：US14575491

申请日：2014-12-18

Applicant: RF Micro Devices, Inc.

Inventor： Christopher Truong Ngo ,  Alexander Wayne Hietala ,  Christian Rye Iversen ,  Ruediger Bauder

IPC: G06F13/00 ,  G06F13/362 ,  G06F13/42

Abstract: A bus interface system is disclosed that includes a master bus controller and a slave bus controller that are coupled by a bus line. The slave bus controller includes a decoder that allows for data to be transmitted along just the bus line. The decoder includes an oscillator, a first counter, and a comparison circuit. The oscillator is configured to be enabled by data pulses defined by the input data signal and generate oscillation pulses while enabled. The first counts the oscillation pulses and indicates a number of the oscillation pulses generated during a time slot. The comparison circuit is configured to this number with a reference number and generate a data output that represents a first logical value in response to the number being greater than the reference parameter and represents a second logical value in response to the number being less than the reference parameter.

公开(公告)号：US09225231B2

公开(公告)日：2015-12-29

申请号：US14027416

申请日：2013-09-16

Applicant: RF Micro Devices, Inc.

Inventor： Philippe Gorisse ,  Nadim Khlat ,  Christopher Truong Ngo

IPC: H02M1/14 ,  H02M1/15 ,  H03F1/02 ,  H02M1/00

CPC classification number: H02M1/14 ,  H02M1/15 ,  H02M2001/0045 ,  H03F1/0211 ,  H03F1/0261

Abstract: A direct current (DC)-DC converter, which includes an open loop ripple cancellation circuit, a switching supply, and a parallel amplifier, is disclosed. During a calibration mode, the parallel amplifier provides a parallel amplifier output current to regulate a power supply output voltage based on a calibration setpoint. The switching supply drives the parallel amplifier output current toward zero using a switching control signal, such that during the calibration mode, an estimate of a current gain is based on the switching control signal. Further, during the calibration mode, the open loop ripple cancellation circuit is disabled. During a normal operation mode, the open loop ripple cancellation circuit provides a ripple cancellation current, which is based on the estimate of the current gain.

Abstract translation: 公开了一种直流（DC）-DC转换器，其包括开环纹波消除电路，开关电源和并联放大器。 在校准模式期间，并行放大器提供并行放大器输出电流，以调节基于校准设定值的电源输出电压。 开关电源使用开关控制信号将平行放大器输出电流驱动到零，使得在校准模式期间，电流增益的估计基于开关控制信号。 此外，在校准模式期间，开环纹波消除电路被禁用。 在正常工作模式下，开环纹波消除电路提供纹波消除电流，其基于当前增益的估计。

公开(公告)号：US20150193373A1

公开(公告)日：2015-07-09

申请号：US14659292

申请日：2015-03-16

Applicant: RF Micro Devices, Inc.

Inventor： Christopher Truong Ngo ,  Alexander Wayne Hietala

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/364

CPC classification number: G06F13/4291 ,  G06F13/3625 ,  G06F13/364 ,  G06F13/4018

Abstract: The disclosure relates to bus interface systems. In one embodiment, the bus interface system includes a bus line along with a master bus controller and a slave bus controller coupled to the bus line. In order to start a data frame, the master bus controller is configured to generate a sequence of data pulses along the bus line such that the sequence of data pulses is provided in accordance to a start of sequence (SOS) pulse pattern. The slave bus controller is configured to recognize that the sequence of data transmitted along the bus line by the master bus controller has been provided in accordance with the SOS pulse pattern. In this manner, the slave bus controller can detect when the master bus controller has started a new data frame. As such, the exchange of information through data frames can be synchronized along the bus line with requiring an additional bus line for a clock signal.

Abstract translation: 本公开涉及总线接口系统。 在一个实施例中，总线接口系统包括总线线路以及主总线控制器和耦合到总线线路的从总线控制器。 为了开始数据帧，主总线控制器被配置为沿着总线生成一系列数据脉冲，使得根据序列开始（SOS）脉冲模式提供数据脉冲序列。 从总线控制器被配置为识别主总线控制器沿总线发送的数据序列是根据SOS脉冲模式提供的。 以这种方式，从总线控制器可以检测主总线控制器何时开始新的数据帧。 因此，通过数据帧的信息交换可以沿着总线同步，同时需要用于时钟信号的附加总线。

公开(公告)号：US20140304442A1

公开(公告)日：2014-10-09

申请号：US14160900

申请日：2014-01-22

Applicant: RF Micro Devices, Inc.

Inventor： Alexander Wayne Hietala ,  Christopher Truong Ngo ,  Eric K. Bolton

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  Y02D10/14 ,  Y02D10/151

Abstract: Disclosed is a digital communication control system having a serial bus buffer that includes a primary interface adapted to support serial communication over a primary bus, a buffered interface adapted to support serial communication over a buffered bus, and a controller coupled between the primary bus and the buffered bus. The primary bus is coupled to a first device and at least one second device and the buffered bus is coupled to at least one third device. The controller is adapted to receive a first data signal and a clock signal at the primary interface and replicate the first data signal and the clock signal at the buffered interface.

Abstract translation: 公开了一种具有串行总线缓冲器的数字通信控制系统，该串行总线缓冲器包括适于支持通过主总线的串行通信的主接口，适于支持通过缓冲总线的串行通信的缓冲接口以及耦合在主总线与 缓冲总线。 主总线耦合到第一设备和至少一个第二设备，并且缓冲总线耦合到至少一个第三设备。 控制器适于在主接口处接收第一数据信号和时钟信号，并在缓冲接口处复制第一数据信号和时钟信号。

公开(公告)号：US20140055197A1

公开(公告)日：2014-02-27

申请号：US14072140

申请日：2013-11-05

Applicant: RF Micro Devices, Inc.

Inventor： Nadim Khlat ,  Michael R. Kay ,  Phillippe Gorisse ,  Christopher Truong Ngo

IPC: H03G3/30

CPC classification number: H03G3/3042 ,  H02M3/07 ,  H02M3/158 ,  H02M2001/0032 ,  H03F1/0227 ,  H03F3/24 ,  H03F3/45663 ,  Y02B70/16

Abstract: A power management system, which includes a parallel amplifier circuit and a switch mode power supply converter, is disclosed. The switch mode power supply converter cooperatively operates with the parallel amplifier circuit to form the power management system. The power management system operates in one of a high power modulation mode, a medium power modulation mode, and a low power average power tracking mode. Further, during the high power modulation mode and the medium power modulation mode, the power management system controls a power amplifier supply voltage to a radio frequency power amplifier to provide envelope tracking. During the low power average power tracking mode, the power management system controls the power amplifier supply voltage to the radio frequency power amplifier to provide average power tracking.

Abstract translation: 公开了一种电源管理系统，其包括并联放大器电路和开关模式电源转换器。 开关模式电源转换器与并行放大器电路协同工作，形成电源管理系统。 电源管理系统以高功率调制模式，中等功率调制模式和低功率平均功率跟踪模式之一工作。 此外，在高功率调制模式和中等功率调制模式期间，电力管理系统控制向射频功率放大器的功率放大器电源电压以提供包络跟踪。 在低功率平均功率跟踪模式下，电源管理系统控制功率放大器对射频功率放大器的电源电压，以提供平均功率跟踪。