公开(公告)号：US20190393346A1

公开(公告)日：2019-12-26

申请号：US16352766

申请日：2019-03-13

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L21/266 ,  H01L21/265

Abstract: A metal oxide semiconductor (MOS) device includes: a semiconductor layer, an isolation structure, a well, a gate, a source, a drain, a first lightly doped region, and a second lightly doped region. The first lightly doped region is located right below a spacer layer and a portion of a dielectric layer of the gate. In a channel direction, the first lightly doped region is between and contacts the drain and an inversion current channel. The second lightly doped region includes a first part and a second part. The first part is located right below the spacer which is near the source, and the first part is between and contacts the source and the inversion current channel. The second part is located right below the spacer which is near the drain, and the second part is between and contacts the drain and the first lightly doped region.

公开(公告)号：US10466732B2

公开(公告)日：2019-11-05

申请号：US16274162

申请日：2019-02-12

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Chien-Yu Chen ,  Tsung-Yi Huang ,  Ting-Wei Liao

IPC: H02M3/156 ,  H02H9/04 ,  G05F3/22 ,  H03K19/003 ,  H03K17/22

Abstract: A switching regulator includes a power stage circuit and a control circuit. The power stage circuit operates a high-side switch and a low-side switch therein according to a high-side signal and a low-side signal respectively to generate an inductor current flowing through an inductor therein. The adjustment signal generation circuit in the control circuit generates an adjustment level according to the high-side signal, the low-side signal, and/or the inductor current, wherein the adjustment level is switched between a reverse recovery level and an anti-latch-up level, and is electrically connected to a low-side isolation region of the low-side switch. The reverse recovery level is lower than the input voltage. The anti-latch-up level is higher than the reverse recovery level to avoid a latch-up effect.

公开(公告)号：US10236375B2

公开(公告)日：2019-03-19

申请号：US15889051

申请日：2018-02-05

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chu-Feng Chen

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265 ,  H01L21/762 ,  H01L21/266

Abstract: A high voltage MOS device includes: a well region with a first conductive type, a body region with a second conductive type, a gate, plural source regions with the first conductive type, a drain region with the first conductive type, and a body contact region with the second conductive type. The plural source regions contact the gate, and are substantially arranged in parallel along a width direction, and each two neighboring source regions are not contacted with each other. The body connection region extends along the width direction and overlaps with at least two of the source regions, such that the body connection region includes at least a first region and a second region, wherein the first region overlaps with at least one of the source regions, and the second region does not overlap any of the regions. The contact region does not contact the gate along a lateral direction.

公开(公告)号：US20190067471A1

公开(公告)日：2019-02-28

申请号：US16057725

申请日：2018-08-07

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L29/7816 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/761 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/08 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/42368 ,  H01L29/66 ,  H01L29/66681 ,  H01L29/66689

Abstract: A high voltage device is formed in a semiconductor substrate, and includes: a first deep well, a lateral lightly doped region, a high voltage well, an isolation region, a body region, a gate, a source, a drain, and a first isolation well. The first deep well and the first isolation well are for electrical isolating the high voltage device from neighboring devices below a top surface of the semiconductor substrate. The lateral lightly doped region is located between the first deep well and the high voltage well in a vertical direction, and the lateral lightly doped region contacts the first deep well and the high voltage well. The lateral lightly doped region is for reducing an inner capacitance of the high voltage device when the high voltage device operates, to improve transient response.

公开(公告)号：US20180342612A1

公开(公告)日：2018-11-29

申请号：US16038015

申请日：2018-07-17

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7816 ,  H01L21/76205 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681

Abstract: A high-side device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, and a buried region. A channel junction is formed between the body region and the high voltage well. The buried region is formed in the substrate and the epitaxial layer, and in a vertical direction, a part of the buried region is located in the substrate and another part of the buried region is located in the epitaxial layer. In the channel direction, an inner side boundary of the buried region is between the drain and the channel junction. An impurity concentration of a second conductive type of the buried region is sufficient to prevent the high voltage well between the channel junction and the drain from being completely depleted when the high-side power device operates in a conductive operation. A corresponding manufacturing method is also disclosed.

公开(公告)号：US20180331211A1

公开(公告)日：2018-11-15

申请号：US15889051

申请日：2018-02-05

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang ,  Chu-Feng Chen

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/76202 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A high voltage MOS device includes: a well region with a first conductive type, a body region with a second conductive type, a gate, plural source regions with the first conductive type, a drain region with the first conductive type, and a body contact region with the second conductive type. The plural source regions contact the gate, and are substantially arranged in parallel along a width direction, and each two neighboring source regions are not contacted with each other. The body connection region extends along the width direction and overlaps with at least two of the source regions, such that the body connection region includes at least a first region and a second region, wherein the first region overlaps with at least one of the source regions, and the second region does not overlap any of the regions. The contact region does not contact the gate along a lateral direction.

公开(公告)号：US20180269319A1

公开(公告)日：2018-09-20

申请号：US15624646

申请日：2017-06-15

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Kun-Huang Yu ,  Tsung-Yi Huang

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: The invention provides a high voltage device, including: an operation layer, formed on a substrate; a body region and a well, formed in the operation layer to connect the top surface, wherein a PN interface is formed between the body region and the well; a gate, formed on the top surface; a drain and a source, the source formed in a portion of the operation layer in the body region, and the drain formed in a portion of the operation layer in the well; a pseudo-gate, formed on the top surface between the gate and the drain; a first resist protection oxide layer, formed on the gate, the well, and the pseudo-gate; a first conductor layer, formed on the first resist protection oxide layer; a second resist protection oxide layer, formed on the pseudo-gate and the well, the second resist protection oxide layer having no contact with the first resist protection oxide layer; and a second conductor layer, formed on the second resist protection oxide layer.

公开(公告)号：US10056480B2

公开(公告)日：2018-08-21

申请号：US15192741

申请日：2016-06-24

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Yi Huang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/7816 ,  H01L21/76205 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681

Abstract: A high-side device includes: a substrate, an epitaxial layer, a high voltage well, a body region, a gate, a source, a drain, and a buried region. A channel junction is formed between the body region and the high voltage well. The buried region is formed in the substrate and the epitaxial layer, and in a vertical direction, a part of the buried region is located in the substrate and another part of the buried region is located in the epitaxial layer. In the channel direction, an inner side boundary of the buried region is between the drain and the channel junction. An impurity concentration of a second conductive type of the buried region is sufficient to prevent the high voltage well between the channel junction and the drain from being completely depleted when the high-side power device operates in a conductive operation. A corresponding manufacturing method is also disclosed.

公开(公告)号：US20180191247A1

公开(公告)日：2018-07-05

申请号：US15587742

申请日：2017-05-05

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Kuo-Hsuan Lo ,  Tsung-Yi Huang

IPC: H02M3/156 ,  H01L29/739 ,  H01L29/10 ,  H01L29/872

CPC classification number: H01L29/7395 ,  H01L29/0619 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/782 ,  H01L29/7835 ,  H01L29/872

Abstract: The invention provides a power device, which includes: an operation layer, including a top surface, a body region and a drift region, the body region and the drift region being connected in a lateral direction, to form a PN junction along a channel width direction between the body region and the drift region; a gate, formed on the top surface, and the PN junction is located under the gate; a source, formed in a portion of the operation layer between the body region and the top surface; a drain, formed in another portion of the operation layer between the drift region and the top surface; a first conduction portion, formed on the top surface for electrically connecting the source; a conduction layer, formed on the first conduction portion and electrically connected to the source via the first conduction portion; and a second conduction portion, formed on the top surface and between the conduction layer and the drift region in a thickness direction, for electrically connecting the drift region and the conduction layer, wherein a Schottky diode is formed by the second conduction portion and the drift region.

公开(公告)号：US09853100B1

公开(公告)日：2017-12-26

申请号：US15490662

申请日：2017-04-18

Applicant: RICHTEK TECHNOLOGY CORPORATION

Inventor： Tsung-Ying Tsai ,  Kun-Hun You ,  Tsung-Yi Huang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/063 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

Abstract: The present invention provides a high voltage device and manufacturing method thereof. The high voltage device includes: a semiconductor substrate, an isolation structure, a gate, a body region, a well, a source, a drain and a lightly doped diffusion (LDD) region. The isolation structure is formed on an upper surface of the semiconductor substrate, for defining a device region, The LDD region is formed on the well in the device region. In a lateral direction, the LDD region is located between the gate and the drain, and the LDD region is not in direct contact with the drain.